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A parameterised genetic algorithm IP core: FPGA design, implementation and performance evaluation

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dc.contributor.author Deliparaschos, KM en
dc.contributor.author Doyamis, GC en
dc.contributor.author Tzafestas, SG en
dc.date.accessioned 2014-03-01T01:27:46Z
dc.date.available 2014-03-01T01:27:46Z
dc.date.issued 2008 en
dc.identifier.issn 0020-7217 en
dc.identifier.uri http://hdl.handle.net/123456789/18567
dc.subject Field programmable gate array chip en
dc.subject Genetic algorithm en
dc.subject Intellectual property core en
dc.subject Travelling salesman problem en
dc.subject Very high-speed integrated-circuits description language en
dc.subject.classification Engineering, Electrical & Electronic en
dc.subject.other Algorithms en
dc.subject.other Benchmarking en
dc.subject.other Boolean functions en
dc.subject.other Field programmable gate arrays (FPGA) en
dc.subject.other Genetic algorithms en
dc.subject.other Intellectual property en
dc.subject.other Linguistics en
dc.subject.other Logic gates en
dc.subject.other Optical sensors en
dc.subject.other Population statistics en
dc.subject.other Speed en
dc.subject.other And performance evaluations en
dc.subject.other Benchmarking functions en
dc.subject.other Bit resolutions en
dc.subject.other Crossover and mutations en
dc.subject.other Field programmable gate array chip en
dc.subject.other Field programmable gate arrays en
dc.subject.other Fpga designs en
dc.subject.other Frequency rates en
dc.subject.other Hardware description languages en
dc.subject.other Intellectual property core en
dc.subject.other Intellectual property cores en
dc.subject.other IP cores en
dc.subject.other Mutation probabilities en
dc.subject.other Natural selections en
dc.subject.other Optimisation en
dc.subject.other Parameterisation en
dc.subject.other Place and routes en
dc.subject.other Proposed architectures en
dc.subject.other Random searches en
dc.subject.other Real-time applications en
dc.subject.other Software versions en
dc.subject.other Speed-ups en
dc.subject.other Travelling salesman problem en
dc.subject.other Travelling salesman problems en
dc.subject.other Very high-speed integrated-circuits description language en
dc.subject.other Computer hardware description languages en
dc.title A parameterised genetic algorithm IP core: FPGA design, implementation and performance evaluation en
heal.type journalArticle en
heal.identifier.primary 10.1080/00207210802387494 en
heal.identifier.secondary http://dx.doi.org/10.1080/00207210802387494 en
heal.language English en
heal.publicationDate 2008 en
heal.abstract Genetic algorithm (GA) is a directed random search technique working on a population of solutions and is based on natural selection. However, its convergence to the optimum may be very slow for complex optimisation problems, especially when the GA is software-implemented, making it difficult to be used in real-time applications. In this article, a parameterised GA intellectual property core is designed and implemented on hardware, achieving impressive time-speedups when compared to its software version. The parameterisation stands for the number of population individuals and their bit resolution, the bit resolution of each individual's fitness, the number of elite genes in each generation, the crossover and mutation methods, the maximum number of generations, the mutation probability and its bit resolution. The proposed architecture is implemented in a field programmable gate array chip with the use of a very high-speed integrated-circuits hardware description language and advanced synthesis and place and route tools. The GA discussed in this work achieves a frequency rate of 92MHz and is evaluated using the 'travelling salesman problem' as well as several benchmarking functions. en
heal.publisher TAYLOR & FRANCIS LTD en
heal.journalName International Journal of Electronics en
dc.identifier.doi 10.1080/00207210802387494 en
dc.identifier.isi ISI:000259975000004 en
dc.identifier.volume 95 en
dc.identifier.issue 11 en
dc.identifier.spage 1149 en
dc.identifier.epage 1166 en


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