A tabu-based partitioning and layer assignment algorithm for 3-D FPGAs

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dc.contributor.author Siozios, K en
dc.contributor.author Soudris, D en
dc.date.accessioned 2014-03-01T01:35:03Z
dc.date.available 2014-03-01T01:35:03Z
dc.date.issued 2011 en
dc.identifier.issn 19430663 en
dc.identifier.uri http://hdl.handle.net/123456789/20950
dc.subject Computer-aided design (CAD) tool en
dc.subject field-programmable gate array (FPGA) en
dc.subject partitioning algorithm en
dc.subject three-dimensional (3-D) architectures en
dc.subject.other Chip stacking en
dc.subject.other Computer aided design tools en
dc.subject.other Consumer electronics products en
dc.subject.other Form factors en
dc.subject.other Layer assignment en
dc.subject.other Lower-power consumption en
dc.subject.other Partitioning algorithms en
dc.subject.other Semiconductor technology en
dc.subject.other Threedimensional (3-d) en
dc.subject.other Algorithms en
dc.subject.other Approximation theory en
dc.subject.other Axial flow en
dc.subject.other Computer aided design en
dc.subject.other Consumer electronics en
dc.subject.other Field programmable gate arrays (FPGA) en
dc.subject.other Semiconductor device manufacture en
dc.subject.other Three dimensional en
dc.title A tabu-based partitioning and layer assignment algorithm for 3-D FPGAs en
heal.type journalArticle en
heal.identifier.primary 10.1109/LES.2011.2161571 en
heal.identifier.secondary http://dx.doi.org/10.1109/LES.2011.2161571 en
heal.identifier.secondary 5961607 en
heal.publicationDate 2011 en
heal.abstract Integrating more functionality in a smaller form factor with higher performance and lower power consumption is pushing semiconductor technology scaling to its limits. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronics products. This letter introduces a TSV-aware partitioning algorithm that enables higher performance for application implementation onto 3-D field-programmable gate arrays (FPGAs). Unlike other algorithms that minimize the number of connections among layers, our solution leads to a more efficient utilization of the available (fabricated) interlayer connectivity. Experimental results show average reductions in delay and power consumption, as compared to similar 3-D computer-aided design (CAD) tools, about 28% and 26%, respectively. © 2011 IEEE. en
heal.journalName IEEE Embedded Systems Letters en
dc.identifier.doi 10.1109/LES.2011.2161571 en
dc.identifier.volume 3 en
dc.identifier.issue 3 en
dc.identifier.spage 97 en
dc.identifier.epage 100 en

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