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A Linear Systolic Array for Real-Time Morphological Image Processing

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dc.contributor.author Diamantaras, KI en
dc.contributor.author Kung, SY en
dc.date.accessioned 2014-03-01T01:45:49Z
dc.date.available 2014-03-01T01:45:49Z
dc.date.issued 1997 en
dc.identifier.issn 13875485 en
dc.identifier.uri http://hdl.handle.net/123456789/24755
dc.relation.uri http://www.scopus.com/inward/record.url?eid=2-s2.0-0031222122&partnerID=40&md5=784604332db22dba9946c478df732b34 en
dc.subject.other Algorithms en
dc.subject.other Computer architecture en
dc.subject.other Image processing en
dc.subject.other Mathematical morphology en
dc.subject.other Parallel processing systems en
dc.subject.other Real time systems en
dc.subject.other Video signal processing en
dc.subject.other Locally parallel globally sequential (LPGS) partitioning en
dc.subject.other Systolic arrays en
dc.title A Linear Systolic Array for Real-Time Morphological Image Processing en
heal.type journalArticle en
heal.publicationDate 1997 en
heal.abstract Mathematical morphology has proven to be a very useful tool for applications such as smoothing, image skeletonization, pattern recognition, machine vision, etc. In this paper we present a 1-dimensional systolic architecture for the basic gray-scale morphology operations: dilation and erosion. Most other morphological operations like opening and closing, are also supported by the architecture since these operations are combinations of the basic ones. The advantages of our design stem from the fact that it has pipeline period α = 1 (i.e., 100% processor utilization), it requires simple communications, and it is exploiting the simplicity of the morphological operations to make it possible to implement them in a linear target machine although the starting algorithm is a generalized 2-D convolution. We also propose a Locally Parallel Globally Sequential (LPGS) partitioning strategy for the best mapping of the algorithm onto the architecture. We conclude that for this particular problem LPGS is better than LSGP in a practical sense (pinout, memory requirement, etc.). Furthermore, we propose a chip design for the basic component of the array that will allow real-time video processing for 8- and 16-bit gray-level frames of size 512 × 512, using only 32 processors in parallel. The design is easily scalable so it can be custom-taylored to fit the requirement of each particular application. en
heal.journalName Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology en
dc.identifier.volume 17 en
dc.identifier.issue 1 en
dc.identifier.spage 43 en
dc.identifier.epage 55 en


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