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A temperature-aware placement and routing algorithm targeting 3D FPGAs

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dc.contributor.author Siozios, K en
dc.contributor.author Soudris, D en
dc.date.accessioned 2014-03-01T01:59:36Z
dc.date.available 2014-03-01T01:59:36Z
dc.date.issued 2010 en
dc.identifier.issn 18684238 en
dc.identifier.uri http://hdl.handle.net/123456789/29001
dc.subject.other CAD tool en
dc.subject.other Clock frequency en
dc.subject.other Critical challenges en
dc.subject.other Energy saving en
dc.subject.other Functional layer en
dc.subject.other Hardware resources en
dc.subject.other High-power en
dc.subject.other Hot spot en
dc.subject.other Hotspots en
dc.subject.other Interconnect structures en
dc.subject.other Maximal values en
dc.subject.other Placement and routing en
dc.subject.other Power Consumption en
dc.subject.other Power densities en
dc.subject.other Power sources en
dc.subject.other Reconfigurable architecture en
dc.subject.other Silicon area en
dc.subject.other Three-dimensional (3D) en
dc.subject.other Algorithms en
dc.subject.other Computer aided design en
dc.subject.other Energy conservation en
dc.subject.other Field programmable gate arrays (FPGA) en
dc.subject.other Programmable logic controllers en
dc.subject.other Reconfigurable hardware en
dc.subject.other Three dimensional en
dc.title A temperature-aware placement and routing algorithm targeting 3D FPGAs en
heal.type journalArticle en
heal.identifier.primary 10.1007/978-3-642-12267-5_12 en
heal.identifier.secondary http://dx.doi.org/10.1007/978-3-642-12267-5_12 en
heal.publicationDate 2010 en
heal.abstract In current reconfigurable architectures, the interconnect structures increasingly contribute to the delay and power consumption budget. The demand for increased clock frequencies and logic availability (smaller area foot print) makes the problem even more important, leading among others to rapid elevation in power density. Three-dimensional (3D) architectures are able to alleviate this problem by accommodating a number of functional layers, each of which might be fabricated in different technology. Since power consumption is a critical challenge for implementing applications onto reconfigurable hardware, a novel temperature-aware placement and routing (P&R) algorithm targeting 3D FPGAs, is introduced. The proposed algorithm achieves to redistribute the switched capacitance over identical hardware resources in a rather ""balanced"" profile, reducing among others the number of hotspot regions, the maximal values of power sources at hotspots, as well as the percentage of device area that consumes high power. For evaluation purposes, the proposed approach is realized as a new CAD tool, named 3DPRO (3D-Placement-and-Routing-Optimization), which is part of the complete framework, named 3D MEANDER. Comparing to alternative solutions, the proposed one reduces the percentage of silicon area that operates under high power by 63%, while it leads to energy savings (about 9%), with an almost negligible penalty in application's delay ranging from 1% up to 5%. © 2010 IFIP International Federation for Information Processing. en
heal.journalName IFIP Advances in Information and Communication Technology en
dc.identifier.doi 10.1007/978-3-642-12267-5_12 en
dc.identifier.volume 313 en
dc.identifier.spage 211 en
dc.identifier.epage 231 en


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