Design of a transceiver for packet video communication on an integrated services network

DSpace/Manakin Repository

Show simple item record

dc.contributor.author Andreatos, A en
dc.contributor.author De Grandi, G en
dc.contributor.author Protonotarios, E en
dc.date.accessioned 2014-03-01T02:40:55Z
dc.date.available 2014-03-01T02:40:55Z
dc.date.issued 1989 en
dc.identifier.uri http://hdl.handle.net/123456789/30280
dc.subject Delay Jitter en
dc.subject Digital Video en
dc.subject Hardware Implementation en
dc.subject Integrated Services en
dc.subject Integrated Services Networks en
dc.subject Packet Networks en
dc.subject Packet Video en
dc.subject System Evaluation en
dc.subject System Performance en
dc.subject Digital To Analog Converter en
dc.subject.other Data Transmission--Packet Switching en
dc.subject.other Digital Communication Systems en
dc.subject.other Television Receivers en
dc.subject.other Television Transmitters en
dc.subject.other Integrated Services Packet Network en
dc.subject.other Packet Video Communication en
dc.subject.other Packet Video Transceiver en
dc.subject.other TV Receiver Local Clock Generator en
dc.subject.other Television Systems, Cable en
dc.title Design of a transceiver for packet video communication on an integrated services network en
heal.type conferenceItem en
heal.identifier.primary 10.1109/MELCON.1989.50111 en
heal.identifier.secondary http://dx.doi.org/10.1109/MELCON.1989.50111 en
heal.publicationDate 1989 en
heal.abstract The authors describe the architecture and give details on the hardware implementation of a special packet video transceiver, which is appropriate for the communication of broadcast television signals between two stations of an integrated services packet network. The system performs line processing and can detect and/or correct various kinds of errors concerning the reception of packets at the receiver, basically by replacing a wrong or missing packet or line by previously received information from the preceding scan line. Additional information is given about the design and operation of a special frequency-regulation system which the receiver uses to trigger a video digital-to-analog converter which reconverts the digitized video signal into analog form, as well as for a master clock source. This system evaluates the transmitter scanning frequency, basing the evaluation on the timing of the incoming packets. These packets are transmitted through a noisy channel (isochronous network) and are affected by random but bounded delay (jitter). en
heal.publisher Publ by IEEE, Piscataway, NJ, United States en
heal.journalName [No source information available] en
dc.identifier.doi 10.1109/MELCON.1989.50111 en
dc.identifier.spage 577 en
dc.identifier.epage 582 en

Files in this item

Files Size Format View

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record