Efficient shared-buffer for high speed ATM networks

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dc.contributor.author Konstantoulakis, G en
dc.contributor.author Pramataris, K en
dc.contributor.author Reisis, D en
dc.contributor.author Stassinopoulos, G en
dc.date.accessioned 2014-03-01T02:41:10Z
dc.date.available 2014-03-01T02:41:10Z
dc.date.issued 1996 en
dc.identifier.uri http://hdl.handle.net/123456789/30402
dc.subject Atm Networks en
dc.subject Data Stream en
dc.subject High Speed en
dc.subject Network Connectivity en
dc.subject Packet Networks en
dc.subject Point of View en
dc.subject.other Buffer circuits en
dc.subject.other Multiplexing equipment en
dc.subject.other Packet networks en
dc.subject.other Shared buffer components en
dc.subject.other Asynchronous transfer mode en
dc.title Efficient shared-buffer for high speed ATM networks en
heal.type conferenceItem en
heal.identifier.primary 10.1109/ICECS.1996.584477 en
heal.identifier.secondary http://dx.doi.org/10.1109/ICECS.1996.584477 en
heal.publicationDate 1996 en
heal.abstract This paper describes an efficient Shared-Buffer component suitable for high-speed ATM networks. The component stores incoming ATM cells into individual virtual linked lists, according to the network connection that the cell belongs to. All linked lists are realized utilizing a single memory component, thus achieving maximal memory utilization. Furthermore, using the proposed buffering technique, it is feasible to control and monitor buffered data on a per connection basis, enabling network nodes to perform sophisticated policing and control functions on the incoming data streams. Although the particular component has been designed for ATM networks, the proposed buffering architecture can be efficiently used in other packet networks as well. The Shared-Buffer component, which has been used in an existent ATM multiplexer, is presented from an implementation point of view and specific ideas, concerning hardware realization of it, are given. Furthermore, additional features that the component can support are presented along with hardware realization. Some possible utilization scenarios, where the component could be efficiently used, are finally presented. en
heal.publisher IEEE, Piscataway, NJ, United States en
heal.journalName Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems en
dc.identifier.doi 10.1109/ICECS.1996.584477 en
dc.identifier.volume 2 en
dc.identifier.spage 776 en
dc.identifier.epage 779 en

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