A hardware extension of the RISC microprocessor for attribute grammar evaluation

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dc.contributor.author Panagopoulos, I en
dc.contributor.author Pavlatos, C en
dc.contributor.author Papakonstantinou, G en
dc.date.accessioned 2014-03-01T02:42:23Z
dc.date.available 2014-03-01T02:42:23Z
dc.date.issued 2004 en
dc.identifier.uri http://hdl.handle.net/123456789/30981
dc.subject Attribute Grammars en
dc.subject Declarative programs en
dc.subject RISC microprocessors en
dc.subject.other Attribute grammars en
dc.subject.other Declarative programs en
dc.subject.other Hardware extension en
dc.subject.other RISC microprocessors en
dc.subject.other Benchmarking en
dc.subject.other Computational methods en
dc.subject.other Computer hardware en
dc.subject.other Computer programming en
dc.subject.other Mathematical transformations en
dc.subject.other Program compilers en
dc.subject.other Semantics en
dc.subject.other Trees (mathematics) en
dc.subject.other Microprocessor chips en
dc.title A hardware extension of the RISC microprocessor for attribute grammar evaluation en
heal.type conferenceItem en
heal.identifier.primary 10.1145/967900.968081 en
heal.identifier.secondary http://dx.doi.org/10.1145/967900.968081 en
heal.publicationDate 2004 en
heal.abstract Conventional implementations of Attribute Grammar (AG) evaluators in embedded systems today, are solely of software nature. A compiler transforms the parser's specification along with the declarative attribute evaluation rules into a behaviorally equivalent procedural program to be executed on the microprocessor. This approach affects the final system's performance as well as the complexity of the final implementation. Efforts in presenting hardware implementations of AG evaluators, although efficient enough in terms of performance, are usually fully implemented in hardware and as a consequence restricted to a single application. We exploit HW/SW codesign methods in the effort of presenting a hardware implementation of AG evaluators that is both reprogrammable and increases the desired system's performance. We achieve that by extending a conventional RISC microprocessor by combining it with a programmable implementation of a hardware parser to propose a fully programmable AG evaluator that supports the execution of hybrid combinations of declarative-procedural code. The hardware parser increases design efficiency of tree derivations while the RISC microprocessor handles the attribute evaluation computations. As a result, performance is increased while design flexibility required in embedded system applications is preserved. en
heal.journalName Proceedings of the ACM Symposium on Applied Computing en
dc.identifier.doi 10.1145/967900.968081 en
dc.identifier.volume 1 en
dc.identifier.spage 897 en
dc.identifier.epage 904 en

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