Recent advances in nanoparticle memories

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dc.contributor.author Tsoukalas, D en
dc.contributor.author Dimitrakis, P en
dc.contributor.author Kolliopoulou, S en
dc.contributor.author Normand, P en
dc.date.accessioned 2014-03-01T02:43:29Z
dc.date.available 2014-03-01T02:43:29Z
dc.date.issued 2005 en
dc.identifier.issn 0921-5107 en
dc.identifier.uri http://hdl.handle.net/123456789/31439
dc.subject CMOS en
dc.subject Nanoparticle en
dc.subject Non-volatile memory en
dc.subject Self-assembly en
dc.subject.classification Materials Science, Multidisciplinary en
dc.subject.classification Physics, Condensed Matter en
dc.subject.other Chemical vapor deposition en
dc.subject.other CMOS integrated circuits en
dc.subject.other Data storage equipment en
dc.subject.other Electric potential en
dc.subject.other Energy absorption en
dc.subject.other Ion implantation en
dc.subject.other Molecular beam epitaxy en
dc.subject.other Semiconductor devices en
dc.subject.other Sputtering en
dc.subject.other CMOS en
dc.subject.other Metallic nanoparticles en
dc.subject.other Nanoparticle en
dc.subject.other Non-volatile memory en
dc.subject.other Nanostructured materials en
dc.title Recent advances in nanoparticle memories en
heal.type conferenceItem en
heal.identifier.primary 10.1016/j.mseb.2005.08.105 en
heal.identifier.secondary http://dx.doi.org/10.1016/j.mseb.2005.08.105 en
heal.language English en
heal.publicationDate 2005 en
heal.abstract Nanoparticle memories have made their point during last years as a possible solution to overcome the scaling issue of electronic non-volatile memories. Ultimately, we are looking for nanoparticle memories to significantly decrease the voltage needed to write/erase the memory without compromising its retention characteristics. Several approaches have been reported for semiconductor nanoparticle formation using techniques such as chemical vapor deposition, molecular beam epitaxy or sputtering. In the present review emphasis is placed on a silicon nanoparticle memory resulting from low-energy ion implantation of silicon within a thin oxide layer and subsequent annealing. This process allows for the formation of a two-dimensional array of silicon nanoparticles within the gate oxide in one processing step making the process attractive for CMOS integration. Material issues related with ion implantation energy, dose and annealing ambient for optimum device performance are addressed. As an alternative to semiconductor nanoparticles, metallic nanoparticles have been investigated since they have the potential for more versatile engineering of energy barriers that would allow improved data retention for memory devices operating at low voltages. Processing approaches for metallic nanoparticle formation are addressed and corresponding memory device performance is discussed for the particular case of room temperature deposited metallic nanoparticles by chemical methods. (c) 2005 Elsevier B.V. All rights reserved. en
heal.publisher ELSEVIER SCIENCE SA en
heal.journalName Materials Science and Engineering B: Solid-State Materials for Advanced Technology en
dc.identifier.doi 10.1016/j.mseb.2005.08.105 en
dc.identifier.isi ISI:000233895800014 en
dc.identifier.volume 124-125 en
dc.identifier.issue SUPPL. en
dc.identifier.spage 93 en
dc.identifier.epage 101 en

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