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High-level synthesis methodologies for delay-area optimized coarse-grained reconfigurable coprocessor architectures

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dc.contributor.author Xydis, S en
dc.contributor.author Pekmestzi, K en
dc.contributor.author Soudris, D en
dc.contributor.author Economakos, G en
dc.date.accessioned 2014-03-01T02:46:49Z
dc.date.available 2014-03-01T02:46:49Z
dc.date.issued 2010 en
dc.identifier.uri http://hdl.handle.net/123456789/32876
dc.subject Automated Design en
dc.subject Coarse Grained en
dc.subject Design Methodology en
dc.subject High Level Synthesis en
dc.subject High Performance en
dc.subject Levels of Abstraction en
dc.subject Optimal Design en
dc.subject reconfigurable architecture en
dc.subject reconfigurable computing en
dc.subject reconfigurable system en
dc.subject System Architecture en
dc.subject Very Large Scale Integrated en
dc.subject.other Area efficiency en
dc.subject.other Area optimized en
dc.subject.other Automated design en
dc.subject.other Automated synthesis en
dc.subject.other Co-processor architecture en
dc.subject.other Coarse-grained en
dc.subject.other Computing devices en
dc.subject.other Data-paths en
dc.subject.other Design Methodology en
dc.subject.other Design procedure en
dc.subject.other Design requirements en
dc.subject.other Design solutions en
dc.subject.other Efficient designs en
dc.subject.other Fundamental design en
dc.subject.other Hardware sharing en
dc.subject.other High Level Synthesis en
dc.subject.other Level of abstraction en
dc.subject.other PhD thesis en
dc.subject.other Process Technologies en
dc.subject.other Re-configurable en
dc.subject.other Reconfigurable computing en
dc.subject.other Reconfigurable systems en
dc.subject.other Scale down en
dc.subject.other System architectures en
dc.subject.other System levels en
dc.subject.other Transistor size en
dc.subject.other Very large-scale integration en
dc.subject.other Word level en
dc.subject.other Architecture en
dc.subject.other Electric power supplies to apparatus en
dc.subject.other Optimization en
dc.subject.other Structural design en
dc.title High-level synthesis methodologies for delay-area optimized coarse-grained reconfigurable coprocessor architectures en
heal.type conferenceItem en
heal.identifier.primary 10.1109/ISVLSI.2010.8 en
heal.identifier.secondary http://dx.doi.org/10.1109/ISVLSI.2010.8 en
heal.identifier.secondary 5572829 en
heal.publicationDate 2010 en
heal.abstract As Very Large Scale Integration (VLSI) process technology continues to scale down transistor sizes, modern computing devices are becoming extremely complex. In order to face this complexity explosion, the shifting of design methodologies towards higher level of abstraction has been proposed. This high level view of the design procedure enables the automated synthesis of applications' architecture that is written in an application-level description i.e. C/C++. Additionally, it allows designers to explore the tradeoffs between different system and implementation parameters to conclude in an efficient design solution. The work done during this PhD thesis targets the exploration and optimization of the design solutions in a global manner, by focusing on the combined development of novel (i) system-level automated design methodologies/tools and (ii) circuit-level techniques for a specific class of system architectures - reconfigurable systems. Reconfigurable Computing has been proposed as a new paradigm to address the conflicting design requirements for high performance and area efficiency. Towards this direction, fine- and coarse-grained reconfigurable coprocessor architectures have been presented [1]. Unlike fine-grained, coarse-grained architectures (CGA) operate at the word level of granularity exhibiting better power and performance features, close to ASIC solutions [1]. However, a performance-area-power gap still exists for CGAs to overcome ASIC implementations [2]. Thus, new fundamental design problems/questions has been raised. Does this gap be a bridgeable one? How can CGAs shift even closer to ASIC datapaths? In order to address the aforementioned problems, we identified that hardware sharing at the bit-level generates CGAs with performance and area characteristics closer to ASICs than the existing ones. Thus, this thesis proposes new architectural templates and the corresponding high level synthesis methodologies to enable a new shifting on the state-of-the-art of CGAs. © 2010 IEEE. en
heal.journalName Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010 en
dc.identifier.doi 10.1109/ISVLSI.2010.8 en
dc.identifier.spage 486 en
dc.identifier.epage 487 en


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