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Reconfiguring processor arrays using multiple-track models

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dc.contributor.author Varvarigou, T en
dc.contributor.author Roychowdhury, V en
dc.contributor.author Kailath, T en
dc.date.accessioned 2014-03-01T02:47:59Z
dc.date.available 2014-03-01T02:47:59Z
dc.date.issued 1991 en
dc.identifier.uri http://hdl.handle.net/123456789/33483
dc.subject Efficient Algorithm en
dc.subject reconfigurable processor en
dc.title Reconfiguring processor arrays using multiple-track models en
heal.type conferenceItem en
heal.identifier.primary 10.1109/ICWSI.1991.151732 en
heal.identifier.secondary http://dx.doi.org/10.1109/ICWSI.1991.151732 en
heal.publicationDate 1991 en
heal.abstract The authors study a 3-track-1-spare model that has three tracks along each channel and one spare row or column along each boundary. It is shown that the model uses the spare processors very efficiently; specifically, it is proved that a 3-track-1-spare model can support any set of nonintersecting compensation paths. This provides theoretical justification of the observations made in the en
heal.journalName International Conference on Wafer Scale Integration en
dc.identifier.doi 10.1109/ICWSI.1991.151732 en


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