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100% Operational efficient bit-serial programmable fir digital filters

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dc.contributor.author Kalivas, P en
dc.contributor.author Tsirikos, A en
dc.contributor.author Bougas, P en
dc.contributor.author Pekmestzi, KZ en
dc.date.accessioned 2014-03-01T02:49:58Z
dc.date.available 2014-03-01T02:49:58Z
dc.date.issued 2005 en
dc.identifier.uri http://hdl.handle.net/123456789/34835
dc.relation.uri http://www.scopus.com/inward/record.url?eid=2-s2.0-84863662318&partnerID=40&md5=2bc9098482a253392d942019249cb311 en
dc.subject.other Bit-parallel en
dc.subject.other Bit-serial en
dc.subject.other Filter input en
dc.subject.other Filter output en
dc.subject.other FIR digital filters en
dc.subject.other Hardware complexity en
dc.subject.other Input datas en
dc.subject.other Intermediate results en
dc.subject.other Internal registers en
dc.subject.other Operational efficiencies en
dc.subject.other Digital filters en
dc.subject.other Hardware en
dc.subject.other Input output programs en
dc.subject.other Signal processing en
dc.subject.other Efficiency en
dc.title 100% Operational efficient bit-serial programmable fir digital filters en
heal.type conferenceItem en
heal.publicationDate 2005 en
heal.abstract A new scheme for the implementation of programmable FIR digital filters with 100% operational efficiency is presented in this paper. The term 100% operational efficiency implies that no zero bits have to be inserted between successive input data words in order the filter input to be synchronized with the filter output. Both the input data and the filter output are in two's complement LSB-first bit-serial form. The coefficients are in two's complement bit-parallel form. All the intermediate results and the filter output are produced and handled in full precision. The proposed scheme is based on a special serial-parallel multiplier that operates with 100% efficiency. We exploit the internal registers and the free accumulation input in this multiplier to reduce the hardware complexity of the filter significantly. The proposed scheme is compared from the aspect of hardware complexity and efficiency with other bit-serial schemes. en
heal.journalName 13th European Signal Processing Conference, EUSIPCO 2005 en
dc.identifier.spage 1786 en
dc.identifier.epage 1789 en


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