A parameterized genetic algorithm ip core design and implementation

Deliparaschos, KM; Doyamis, GC; Tzafestas, SG

dc.contributor.author	Deliparaschos, KM	en
dc.contributor.author	Doyamis, GC	en
dc.contributor.author	Tzafestas, SG	en
dc.date.accessioned	2014-03-01T02:44:23Z
dc.date.available	2014-03-01T02:44:23Z
dc.date.issued	2007	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31797
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-67149114956&partnerID=40&md5=e429784ad6412f1860b3cebbe3bd0447	en
dc.relation.uri	http://www.informatik.uni-trier.de/~ley/db/conf/icinco/icinco2007-icso.html#DeliparaschosDT07	en
dc.subject	Field programmable gate array (fpga) chip	en
dc.subject	Genetic algorithm (ga)	en
dc.subject	Intellectual property (ip) core	en
dc.subject	Travelling salesman problem (tsp)	en
dc.subject	Very high-speed integrated circuits description language (vhdl)	en
dc.subject.other	Benchmarking functions	en
dc.subject.other	Bit resolution	en
dc.subject.other	Complex optimization	en
dc.subject.other	Crossover and mutation	en
dc.subject.other	Frequency rate	en
dc.subject.other	Hardware description languages	en
dc.subject.other	High-speed integrated circuits	en
dc.subject.other	Intellectual property (ip) core	en
dc.subject.other	Intellectual property cores	en
dc.subject.other	IP core	en
dc.subject.other	Mutation probability	en
dc.subject.other	Natural selection	en
dc.subject.other	Parameterized	en
dc.subject.other	Place and route	en
dc.subject.other	Proposed architectures	en
dc.subject.other	Random searches	en
dc.subject.other	Real-time application	en
dc.subject.other	Software versions	en
dc.subject.other	Travelling salesman problem (tsp)	en
dc.subject.other	Very high-speed integrated circuits description language (vhdl)	en
dc.subject.other	Computer software	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	Genetic algorithms	en
dc.subject.other	Integrated circuits	en
dc.subject.other	Intellectual property	en
dc.subject.other	International law	en
dc.subject.other	Linguistics	en
dc.subject.other	Logic gates	en
dc.subject.other	Optical sensors	en
dc.subject.other	Population statistics	en
dc.subject.other	Robotics	en
dc.subject.other	Traveling salesman problem	en
dc.subject.other	Unmanned vehicles	en
dc.subject.other	Computer hardware description languages	en
dc.title	A parameterized genetic algorithm ip core design and implementation	en
heal.type	conferenceItem	en
heal.publicationDate	2007	en
heal.abstract	Genetic Algorithm (GA) is a directed random search technique working on a population of solutions and based on natural selection. However, its convergence to the optimum may be very slow for complex optimization problems, especially when the GA is software implemented, making it difficult to be used in real time applications. In this paper a parameterized GA Intellectual Property (IP) core is designed and implemented on hardware, achieving impressive time-speedups when compared to its software version. The parameterization stands for the number of population individuals and their bit resolution, the bit resolution of each individual's fitness, the number of elite genes in each generation, the crossover and mutation methods, the maximum number of generations, the mutation probability and its bit resolution. The proposed architecture is implemented in a Field Programmable Gate Array Chip (FPGA) with the use of a Very-HighSpeed Integrated Circuits Hardware Description Language (VHDL) and advanced synthesis and place and route tools. The GA discussed in this work achieves a frequency rate of 92 MIIz and is evaluated using the Traveling Salesman Problem (TSP) as well as several benchmarking functions.	en
heal.journalName	ICINCO 2007 - 4th International Conference on Informatics in Control, Automation and Robotics, Proceedings	en
dc.identifier.volume	ICSO	en
dc.identifier.spage	417	en
dc.identifier.epage	423	en