Flexibility inlining into arithmetic data-paths exploiting a regular interconnection scheme

Xydis, S; Economakos, G; Pekmestzi, K

dc.contributor.author	Xydis, S	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:44:38Z
dc.date.available	2014-03-01T02:44:38Z
dc.date.issued	2007	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31918
dc.subject	Coarse Grained	en
dc.subject	Design Flow	en
dc.subject	Design Technique	en
dc.subject	reconfigurable architecture	en
dc.subject.other	Architecture	en
dc.subject.other	Chemical shift	en
dc.subject.other	Computer systems	en
dc.subject.other	Digital arithmetic	en
dc.subject.other	Electric currents	en
dc.subject.other	Embedded systems	en
dc.subject.other	Magnetic anisotropy	en
dc.subject.other	A-stable	en
dc.subject.other	Average latency	en
dc.subject.other	Coarse Graining	en
dc.subject.other	Computational resources	en
dc.subject.other	Data-paths	en
dc.subject.other	Design flows	en
dc.subject.other	Design techniques	en
dc.subject.other	DSP applications	en
dc.subject.other	Embedded Computer Systems	en
dc.subject.other	Hardware utilization	en
dc.subject.other	Inlining	en
dc.subject.other	International conferences	en
dc.subject.other	Modeling and simulation	en
dc.subject.other	Re-configurable	en
dc.subject.other	Re-configurable architecture	en
dc.subject.other	Computer architecture	en
dc.title	Flexibility inlining into arithmetic data-paths exploiting a regular interconnection scheme	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICSAMOS.2007.4285744	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICSAMOS.2007.4285744	en
heal.identifier.secondary	4285744	en
heal.publicationDate	2007	en
heal.abstract	This paper presents a design technique for coarse grained reconfigurable cores targeting mostly DSP applications. The proposed technique inlines flexibility into custom Carry-Save-Arithmetic (CSA) datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a uniformity transformation imposed on the basic architectures of CSA multipliers and CSA chain-adders/subtractors. The design flow for the implementation of the core is analyzed in detail, and a novel reconfigurable architecture prototype is presented. The paper concludes with the experimental results showing that our architecture performs an average latency reduction of 32.63%, compared with datapaths of primitive computational resources, with a tolerable overhead in hardware utilization. ©2007 IEEE.	en
heal.journalName	Proceedings - 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2007	en
dc.identifier.doi	10.1109/ICSAMOS.2007.4285744	en
dc.identifier.spage	137	en
dc.identifier.epage	144	en