Scaling Issues In An 0.15/spl mu/m CMOS Technology With EKV3.0

Kitonaki, E; Bazigos, A; Bucher, M; Puchner, H; Bhardwaj, S; Papananos, Y

dc.contributor.author	Kitonaki, E	en
dc.contributor.author	Bazigos, A	en
dc.contributor.author	Bucher, M	en
dc.contributor.author	Puchner, H	en
dc.contributor.author	Bhardwaj, S	en
dc.contributor.author	Papananos, Y	en
dc.date.accessioned	2014-03-01T02:50:16Z
dc.date.available	2014-03-01T02:50:16Z
dc.date.issued	2006	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35017
dc.subject	Capacitance Voltage	en
dc.title	Scaling Issues In An 0.15/spl mu/m CMOS Technology With EKV3.0	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/MIXDES.2006.1706557	en
heal.identifier.secondary	http://dx.doi.org/10.1109/MIXDES.2006.1706557	en
heal.publicationDate	2006	en
heal.abstract	Application of the EKV3.0 model to 0.15mum CMOS technology with single poly, and buried channel PMOS, is presented with emphasis on scaling properties of the technology and the model. The EKV3.0 model is illustrated for its fit to NMOS and PMOS drain current, transconductances and output characteristics in weak, moderate and strong inversion over a large temperature range. Scaling properties	en
heal.journalName	Mixed Design of Integrated Circuits and Systems International Conference	en
dc.identifier.doi	10.1109/MIXDES.2006.1706557	en