Application - specific NoC platform design based on System Level Optimization

Papadopoulos, L; Mamagkakis, S; Catthoor, F; Soudris, D

dc.contributor.author	Papadopoulos, L	en
dc.contributor.author	Mamagkakis, S	en
dc.contributor.author	Catthoor, F	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:50:56Z
dc.date.available	2014-03-01T02:50:56Z
dc.date.issued	2007	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35229
dc.subject	Complex Network	en
dc.subject	Dynamic Networks	en
dc.subject	Embedded System	en
dc.subject	Evaluation Metric	en
dc.subject	High Performance	en
dc.subject	Low Power Consumption	en
dc.subject	Multimedia Application	en
dc.subject	Performance Optimization	en
dc.subject	Network On Chip	en
dc.title	Application - specific NoC platform design based on System Level Optimization	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ISVLSI.2007.26	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ISVLSI.2007.26	en
heal.publicationDate	2007	en
heal.abstract	Nowadays, embedded consumer devices execute complex network and multimedia applications that require high performance and low power consumption. Moreover, network-on-chip (NoC) has been proposed as new paradigm for SoC interconnection. For implementing complex applications on NoC platforms, embedded systems require high abstraction level optimizations. To achieve such optimizations, a flexible NoC simulator is needed that provides the essential evaluation metrics.	en
heal.journalName	Annual Symposium on VLSI	en
dc.identifier.doi	10.1109/ISVLSI.2007.26	en