Feasibility of analogue computation for image processing applications

Papananos, Y

dc.contributor.author	Papananos, Y	en
dc.date.accessioned	2014-03-01T01:07:29Z
dc.date.available	2014-03-01T01:07:29Z
dc.date.issued	1989	en
dc.identifier.issn	0956-3768	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/10009
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-0024606174&partnerID=40&md5=6b20d480a9263a0cb6c122aae9c59b2f	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Computers, Analog	en
dc.subject.other	Integrated Circuits, VLSI	en
dc.subject.other	Mathematical Techniques--Algorithms	en
dc.subject.other	Semiconductor Devices, MOS--Applications	en
dc.subject.other	Transistors--Applications	en
dc.subject.other	2D Weighted Averaging Algorithm	en
dc.subject.other	Analog Computation	en
dc.subject.other	Electrical Simulation	en
dc.subject.other	Image Processing	en
dc.title	Feasibility of analogue computation for image processing applications	en
heal.type	journalArticle	en
heal.language	English	en
heal.publicationDate	1989	en
heal.abstract	A processing cell consisting of analogue devices is proposed for the implementation of a 2D weighted averaging algorithm for image processing applications. The major component used is the MOS transistor in CMOS configuration, implementable in VLSI technology. Representative simulation results are given, demonstrating the accuracy of computation and high performance achieved by the proposed circuit. Finally, the desirable features of analogue computation, introduced by the above circuit, are discussed with respect to the corresponding digital circuitry.	en
heal.publisher	IEE-INST ELEC ENG	en
heal.journalName	IEE proceedings. Part G. Electronic circuits and systems	en
dc.identifier.isi	ISI:A1989R995200002	en
dc.identifier.volume	136	en
dc.identifier.issue	1	en
dc.identifier.spage	9	en
dc.identifier.epage	13	en