A new wiring architectUre for parallel processing applications

Papananos, Y

dc.contributor.author	Papananos, Y	en
dc.date.accessioned	2014-03-01T01:07:47Z
dc.date.available	2014-03-01T01:07:47Z
dc.date.issued	1990	en
dc.identifier.issn	0167-9260	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/10161
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-0025491313&partnerID=40&md5=6bd345e35dd64b177e3bfaba94dc9042	en
dc.subject	neural networks	en
dc.subject	Processing array	en
dc.subject	switched-capacitor circuits	en
dc.subject	VLSI	en
dc.subject	wiring model	en
dc.subject.classification	Computer Science, Hardware & Architecture	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Computer Systems, Digital - Parallel Processing	en
dc.subject.other	Neural Networks	en
dc.subject.other	Processing Arrays	en
dc.subject.other	Switched Capacitor Circuits	en
dc.subject.other	Wiring Models	en
dc.subject.other	Computer Architecture	en
dc.title	A new wiring architectUre for parallel processing applications	en
heal.type	journalArticle	en
heal.language	English	en
heal.publicationDate	1990	en
heal.abstract	In this paper, a new architecture for the connection between processing elements in a processing array is proposed. Each PE must be connected to all PEs in a window of size n x n around it. The model is simple and elegant and the introduced reduction in wiring complexity is drastic: it becomes O(n) instead of O(n2) as it would be in the general simple case where all PEs are connected directly to the central PE of the window. On the other hand, the appropriate hardware for the implementation of the proposed technique is very little compared to the whole PE. Further, the utilization factor of the communication channels is evaluated, while a model for the implementation of the PE for a particular algorithm, is proposed, along with the extension of the introduced wiring model in fully interconnected neural networks. © 1990 Elsevier Science Publishers B.V.	en
heal.publisher	ELSEVIER SCIENCE BV	en
heal.journalName	Integration, the VLSI Journal	en
dc.identifier.isi	ISI:A1990EB21500006	en
dc.identifier.volume	10	en
dc.identifier.issue	1	en
dc.identifier.spage	71	en
dc.identifier.epage	88	en