Hardware implementation of partitioned-parallel algorithms in linear prediction

Carayannis, G; Koukoutsis, E; Halkias, CC

dc.contributor.author	Carayannis, G	en
dc.contributor.author	Koukoutsis, E	en
dc.contributor.author	Halkias, CC	en
dc.date.accessioned	2014-03-01T01:08:23Z
dc.date.available	2014-03-01T01:08:23Z
dc.date.issued	1991	en
dc.identifier.issn	0165-1684	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/10449
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-0026221854&partnerID=40&md5=c67c27df05adc69cd2b39b705983b0c8	en
dc.subject	Linear prediction	en
dc.subject	parallel algorithms	en
dc.subject	PARCOR coefficients	en
dc.subject	partitioned-parallel algorithms	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.title	Hardware implementation of partitioned-parallel algorithms in linear prediction	en
heal.type	journalArticle	en
heal.language	English	en
heal.publicationDate	1991	en
heal.abstract	In this paper, a partitioned-parallel strategy for the solution of the Toeplitz equations appearing in the linear prediction case is introduced. From the one extreme, i.e., the use of the Schur recursions for an order recursive implementation with O(1) processors which perform O(p2) MADs (multiplications and divisions), to the other extreme, i.e., the use of the same recursions for a fully parallel implementation with O(p) processors which perform O(p) MADs, there exist a compromise: The hardware designer can 'cut' the computational scheme into suitable partitions, which are executed one after the other, with all the computations of each partition organized in a parallel manner. This way he can achieve increased flexibility, especially in relation to the model order, which can become totally independent of the available number of processors. Moreover, in this paper an abatement methodology is introduced which significantly reduces the number of multiplications of the above computational schemes, as well as the overall algorithm complexity in the case of the parallel design. © 1991.	en
heal.publisher	ELSEVIER SCIENCE BV	en
heal.journalName	Signal Processing	en
dc.identifier.isi	ISI:A1991GH28600001	en
dc.identifier.volume	24	en
dc.identifier.issue	3	en
dc.identifier.spage	253	en
dc.identifier.epage	269	en