Low-latency bit-parallel systolic multiplier

Pekmestzi, KZ; Caraiscos, C

dc.contributor.author	Pekmestzi, KZ	en
dc.contributor.author	Caraiscos, C	en
dc.date.accessioned	2014-03-01T01:09:26Z
dc.date.available	2014-03-01T01:09:26Z
dc.date.issued	1993	en
dc.identifier.issn	0013-5194	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/10987
dc.subject	PARALLEL MULTIPLIERS	en
dc.subject	SYSTOLIC ARRAYS	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Adders	en
dc.subject.other	Arrays	en
dc.subject.other	Digital arithmetic	en
dc.subject.other	Digital signal processing	en
dc.subject.other	Flip flop circuits	en
dc.subject.other	Logic gates	en
dc.subject.other	Parallel processing systems	en
dc.subject.other	VLSI circuits	en
dc.subject.other	Low latency bit parallel systolic multiplier	en
dc.subject.other	Pair wise groupings	en
dc.subject.other	Multiplying circuits	en
dc.title	Low-latency bit-parallel systolic multiplier	en
heal.type	journalArticle	en
heal.identifier.primary	10.1049/el:19930247	en
heal.identifier.secondary	http://dx.doi.org/10.1049/el:19930247	en
heal.language	English	en
heal.publicationDate	1993	en
heal.abstract	A bit-parallel systolic multiplier based on pair-wise grouping of the bit products is presented. The proposed scheme yields significantly lower latency compared to existing systolic multipliers, without increasing the circuit complexity. High throughput is achieved, limited by the delay of a gated full adder and a latch.	en
heal.publisher	IEE-INST ELEC ENG	en
heal.journalName	Electronics Letters	en
dc.identifier.doi	10.1049/el:19930247	en
dc.identifier.isi	ISI:A1993LB76600028	en
dc.identifier.volume	29	en
dc.identifier.issue	4	en
dc.identifier.spage	367	en
dc.identifier.epage	369	en