Pregenerated count-enable counters

Pekmestzi, KZ; Thanasouras, N

dc.contributor.author	Pekmestzi, KZ	en
dc.contributor.author	Thanasouras, N	en
dc.date.accessioned	2014-03-01T01:09:30Z
dc.date.available	2014-03-01T01:09:30Z
dc.date.issued	1993	en
dc.identifier.issn	0020-7217	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/11043
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Computational complexity	en
dc.subject.other	Logic circuits	en
dc.subject.other	Logic gates	en
dc.subject.other	State assignment	en
dc.subject.other	Synchronization	en
dc.subject.other	Pregenerated count enable counters	en
dc.subject.other	Pregenerated count enable technique	en
dc.subject.other	Flip flop circuits	en
dc.title	Pregenerated count-enable counters	en
heal.type	journalArticle	en
heal.identifier.primary	10.1080/00207219308925896	en
heal.identifier.secondary	http://dx.doi.org/10.1080/00207219308925896	en
heal.language	English	en
heal.publicationDate	1993	en
heal.abstract	A technique for implementing counters, with a minimum period equal to the delay of one gate plus the delay of one flip-flop, is described. This technique is based on the concept of the pregenerated count-enable, which is presented first. Then, we apply the concept in the implementation of counters of any length. Finally, we make comparisons between the proposed and conventional design techniques.	en
heal.publisher	TAYLOR & FRANCIS LTD	en
heal.journalName	International Journal of Electronics	en
dc.identifier.doi	10.1080/00207219308925896	en
dc.identifier.isi	ISI:A1993LG94600013	en
dc.identifier.volume	74	en
dc.identifier.issue	6	en
dc.identifier.spage	939	en
dc.identifier.epage	944	en