A CLASS OF SYSTOLIC SERIAL-PARALLEL MULTIPLIERS

PEKMESTZI, KZ; CARAISCOS, CG

dc.contributor.author	PEKMESTZI, KZ	en
dc.contributor.author	CARAISCOS, CG	en
dc.date.accessioned	2014-03-01T01:09:39Z
dc.date.available	2014-03-01T01:09:39Z
dc.date.issued	1994	en
dc.identifier.issn	0020-7217	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/11120
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.title	A CLASS OF SYSTOLIC SERIAL-PARALLEL MULTIPLIERS	en
heal.type	journalArticle	en
heal.identifier.primary	10.1080/00207219408925943	en
heal.identifier.secondary	http://dx.doi.org/10.1080/00207219408925943	en
heal.language	English	en
heal.publicationDate	1994	en
heal.abstract	A scheme for a fully-systolic bit-serial multiplier is presented, based on merging two adjacent cells of an existing semi-systolic multiplier in a single new cell. The multiplier has immediate response and high bit-throughput, limited by the propagation delay of one gated full adder and a latch. A way to increase the word-throughput, while retaining systolicity, is also presented.	en
heal.publisher	TAYLOR & FRANCIS LTD	en
heal.journalName	INTERNATIONAL JOURNAL OF ELECTRONICS	en
dc.identifier.doi	10.1080/00207219408925943	en
dc.identifier.isi	ISI:A1994ND73500010	en
dc.identifier.volume	76	en
dc.identifier.issue	3	en
dc.identifier.spage	463	en
dc.identifier.epage	468	en