Systolic frequency dividers/counters

Pekmestzi, KZ; Thanasouras, N

dc.contributor.author	Pekmestzi, KZ	en
dc.contributor.author	Thanasouras, N	en
dc.date.accessioned	2014-03-01T01:10:19Z
dc.date.available	2014-03-01T01:10:19Z
dc.date.issued	1994	en
dc.identifier.issn	1057-7130	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/11366
dc.subject	Circuit Complexity	en
dc.subject	High Speed	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Binary codes	en
dc.subject.other	Binary sequences	en
dc.subject.other	Bit error rate	en
dc.subject.other	Computational complexity	en
dc.subject.other	Computational methods	en
dc.subject.other	Computer architecture	en
dc.subject.other	Flip flop circuits	en
dc.subject.other	Frequency dividing circuits	en
dc.subject.other	Pipeline processing systems	en
dc.subject.other	Response time (computer systems)	en
dc.subject.other	State assignment	en
dc.subject.other	Systolic arrays	en
dc.subject.other	Clock pulses	en
dc.subject.other	Systolic counters	en
dc.subject.other	Counting circuits	en
dc.title	Systolic frequency dividers/counters	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/82.331551	en
heal.identifier.secondary	http://dx.doi.org/10.1109/82.331551	en
heal.language	English	en
heal.publicationDate	1994	en
heal.abstract	The operation of systolic counters, based on the pipelining of the conventional binary counters, is examined. The application of these circuits in the implementation of frequency dividers/counters is also presented. The proposed systolic counters have small circuit complexity and permit very high speed operation.	en
heal.publisher	IEEE, Piscataway, NJ, United States	en
heal.journalName	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing	en
dc.identifier.doi	10.1109/82.331551	en
dc.identifier.isi	ISI:A1994PV34500010	en
dc.identifier.volume	41	en
dc.identifier.issue	11	en
dc.identifier.spage	775	en
dc.identifier.epage	776	en