Low-Latency bit-Parallel systolic VLSI implementation of FIR digital filters

Caraiscos, CG; Pekmestzi, KZ

dc.contributor.author	Caraiscos, CG	en
dc.contributor.author	Pekmestzi, KZ	en
dc.date.accessioned	2014-03-01T01:12:03Z
dc.date.available	2014-03-01T01:12:03Z
dc.date.issued	1996	en
dc.identifier.issn	1057-7130	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/11932
dc.subject	Fir Digital Filter	en
dc.subject	Low Latency	en
dc.subject	Propagation Delay	en
dc.subject	High Throughput	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Adders	en
dc.subject.other	Flip flop circuits	en
dc.subject.other	Systolic arrays	en
dc.subject.other	VLSI circuits	en
dc.subject.other	Low latency systolic implementation	en
dc.subject.other	Digital filters	en
dc.title	Low-Latency bit-Parallel systolic VLSI implementation of FIR digital filters	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/82.508430	en
heal.identifier.secondary	http://dx.doi.org/10.1109/82.508430	en
heal.language	English	en
heal.publicationDate	1996	en
heal.abstract	A new scheme for a high-throughput and low-latency systolic implementation of FIR digital filters is proposed. The input and output sequences arc in bit-parallel LSB-first bit-skewed form, and the throughput is limited by the propagation delay of a gated full adder and a latch. The bits of a full-bit output sample start coming out of the array three clock cycles after the bits of the corresponding input sample enter the array. © 1996 IEEE.	en
heal.publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC	en
heal.journalName	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing	en
dc.identifier.doi	10.1109/82.508430	en
dc.identifier.isi	ISI:A1996UZ86200008	en
dc.identifier.volume	43	en
dc.identifier.issue	7	en
dc.identifier.spage	529	en
dc.identifier.epage	534	en