Systolic digital filters with reduced latency - Serial implementation

Caraiscos, CGr; Pekmestzi, KZ

dc.contributor.author	Caraiscos, CGr	en
dc.contributor.author	Pekmestzi, KZ	en
dc.date.accessioned	2014-03-01T01:12:21Z
dc.date.available	2014-03-01T01:12:21Z
dc.date.issued	1996	en
dc.identifier.issn	0098-9886	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/12077
dc.subject	Digital Filter	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Digital arithmetic	en
dc.subject.other	Digital signal processing	en
dc.subject.other	Graph theory	en
dc.subject.other	Multiplying circuits	en
dc.subject.other	Signal filtering and prediction	en
dc.subject.other	Systolic arrays	en
dc.subject.other	Bit serial arithmetic	en
dc.subject.other	Digit serial arithmetic	en
dc.subject.other	Latency	en
dc.subject.other	Signal flow graph	en
dc.subject.other	Digital filters	en
dc.title	Systolic digital filters with reduced latency - Serial implementation	en
heal.type	journalArticle	en
heal.identifier.primary	10.1002/(SICI)1097-007X(199607/08)24:4<453::AID-CTA896>3.0.CO;2-F	en
heal.identifier.secondary	http://dx.doi.org/10.1002/(SICI)1097-007X(199607/08)24:4<453::AID-CTA896>3.0.CO;2-F	en
heal.language	English	en
heal.publicationDate	1996	en
heal.abstract	Schemes that implement finite impulse response (FIR) and infinite impulse response (IIR) digital filters when bitserial or digit-serial arithmetic is used are proposed in this paper. The main objective is to obtain reduced latency (minimal latency at the word level) of the filter outputs while maintaining the word rate. Existing schemes (systolic or not) for filters are transferred down to the digit level and regular structures systolic at the bit or digit level are proposed. First a modified representation of a digital filter signal flow-graph appropriate for bit-serial or digit-serial arithmetic is presented. Next we show how the resulting flow-graph can be transformed to lead directly to a systolic implementation at the bit or word level. We aim towards minimizing the latency of the filter response. For this reason we work with bidirectional signal flow-graphs that lead to systolic arrays where data and partial results move in opposite directions, otherwise called two-way pipeline systolic arrays. The multipliers that are used in the implementation of the filters must have low latency themselves. For this reason they have the same two-way pipeline structure. In order to maintain the data word rate, the full-bit output of a multiplier must be rounded by a number of bits equal to the length of the data words. We propose a composite bit-serial multiplier that performs this rounding while preserving low latency and incorporate it in schemes for direct implementation of low-latency high-throughput systolic arrays for FIR and IIR. digital filters. These schemes for bit-serial multipliers and filters are also extended to digit-serial arithmetic.	en
heal.publisher	JOHN WILEY & SONS LTD	en
heal.journalName	International Journal of Circuit Theory and Applications	en
dc.identifier.doi	10.1002/(SICI)1097-007X(199607/08)24:4<453::AID-CTA896>3.0.CO;2-F	en
dc.identifier.isi	ISI:A1996UZ45100001	en
dc.identifier.volume	24	en
dc.identifier.issue	4	en
dc.identifier.spage	453	en
dc.identifier.epage	466	en