Automatic hardware synthesis of nested loops using UET grids and VHDL

Koziris, N; Andronikos, T; Economakos, G; Papakonstantinou, G; Tsanakas, P

dc.contributor.author	Koziris, N	en
dc.contributor.author	Andronikos, T	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Papakonstantinou, G	en
dc.contributor.author	Tsanakas, P	en
dc.date.accessioned	2014-03-01T01:12:38Z
dc.date.available	2014-03-01T01:12:38Z
dc.date.issued	1997	en
dc.identifier.issn	0302-9743	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/12186
dc.subject	UET grid index space	en
dc.subject	optimal makespan	en
dc.subject	optimal mapping	en
dc.subject	number of systolic cells	en
dc.subject	uniform unit dependence vectors	en
dc.subject	VHDL based design automation	en
dc.subject.classification	Computer Science, Theory & Methods	en
dc.subject.other	SYSTOLIC ARRAYS	en
dc.subject.other	ALGORITHMS	en
dc.subject.other	TIME	en
dc.title	Automatic hardware synthesis of nested loops using UET grids and VHDL	en
heal.type	journalArticle	en
heal.identifier.primary	10.1007/BFb0031660	en
heal.identifier.secondary	http://dx.doi.org/10.1007/BFb0031660	en
heal.language	English	en
heal.publicationDate	1997	en
heal.abstract	This paper considers the automatic synthesis of systolic architectures from nested loop algorithmic specifications. The high level input is given in the form of uniform dependence loops with unit dependencies and the target architecture is a multidimensional systolic array with unbounded number of cells. A complete methodology for the hardware synthesis of the resulting architecture, based on VHDL specifications, is presented. This methodology automatically detects all necessary computation and communication elements and produces optimal layouts. The theoretical framework of our method is based on the properties of the generalized UET grids, First, we calculate the optimal makespan for the generalized UET grids and then we establish the minimum number of systolic cells required to achieve the optimal makespan. The complexity of the proposed scheduling algorithm is completely independent of the size of the nested loop and depends only on its dimension, thus being the most efficient (in terms of complexity) known to us. All these methods were implemented and incorporated in an integrated software package which provides the designer with a powerful parallel design environment, from high level algorithmic specifications to low-level (i.e., actual layouts) optimal implementation.	en
heal.publisher	SPRINGER-VERLAG BERLIN	en
heal.journalName	HIGH-PERFORMANCE COMPUTING AND NETWORKING	en
heal.bookName	LECTURE NOTES IN COMPUTER SCIENCE	en
dc.identifier.doi	10.1007/BFb0031660	en
dc.identifier.isi	ISI:000074015300087	en
dc.identifier.volume	1225	en
dc.identifier.spage	888	en
dc.identifier.epage	897	en