The energy efficiency of IRAM architectures

Fromm, R; Perissakis, S; Cardwell, N; Kozyrakis, C; McGaughy, B; Patterson, D; Anderson, T; Yelick, K

dc.contributor.author	Fromm, R	en
dc.contributor.author	Perissakis, S	en
dc.contributor.author	Cardwell, N	en
dc.contributor.author	Kozyrakis, C	en
dc.contributor.author	McGaughy, B	en
dc.contributor.author	Patterson, D	en
dc.contributor.author	Anderson, T	en
dc.contributor.author	Yelick, K	en
dc.date.accessioned	2014-03-01T01:13:27Z
dc.date.available	2014-03-01T01:13:27Z
dc.date.issued	1997	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/12481
dc.subject	Energy Consumption	en
dc.subject	Energy Efficient	en
dc.subject	Low Power	en
dc.subject	Memory Access	en
dc.subject	Memory Hierarchy	en
dc.subject	Satisfiability	en
dc.subject	High Density	en
dc.subject	Logical Process	en
dc.title	The energy efficiency of IRAM architectures	en
heal.type	journalArticle	en
heal.identifier.primary	10.1145/384286.264214	en
heal.identifier.secondary	http://dx.doi.org/10.1145/384286.264214	en
heal.publicationDate	1997	en
heal.abstract	Portable systems demand energy efficiency in order to maximize battery l$e. IRAM architectures, which combine DRAM and aprocessor on the same chip in a DRAMprocess, are more energy efficient than conventional systems. The high density of DRAMpermits a much larger amount of memory on-chip than a traditional SRAM cache design in a logic process. This allows most or all IRAM	en
heal.journalName	ACM Sigarch Computer Architecture News	en
dc.identifier.doi	10.1145/384286.264214	en