dc.contributor.author |
Papageorgiou, G |
en |
dc.contributor.author |
Likas, A |
en |
dc.contributor.author |
Stafylopatis, A |
en |
dc.date.accessioned |
2014-03-01T01:13:31Z |
|
dc.date.available |
2014-03-01T01:13:31Z |
|
dc.date.issued |
1998 |
en |
dc.identifier.issn |
0020-7160 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/12531 |
|
dc.subject |
Boltzmann Machine |
en |
dc.subject |
Cauchy Machine |
en |
dc.subject |
Optimization |
en |
dc.subject |
Parallel computing |
en |
dc.subject.classification |
Mathematics, Applied |
en |
dc.subject.other |
Computational complexity |
en |
dc.subject.other |
Computer architecture |
en |
dc.subject.other |
Data storage equipment |
en |
dc.subject.other |
Mathematical models |
en |
dc.subject.other |
Optimization |
en |
dc.subject.other |
Parallel processing systems |
en |
dc.subject.other |
Problem solving |
en |
dc.subject.other |
Boltzmann machine optimizer |
en |
dc.subject.other |
Hopfield type neural network models |
en |
dc.subject.other |
Neural networks |
en |
dc.title |
A hybrid neural optimization scheme based on parallel updates |
en |
heal.type |
journalArticle |
en |
heal.identifier.primary |
10.1080/00207169808804661 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1080/00207169808804661 |
en |
heal.language |
English |
en |
heal.publicationDate |
1998 |
en |
heal.abstract |
A synchronous Hopfield-type neural network model containing units with analog input and binary output. which is suitable for parallel implementation, is examined in the context of solving discrete optimization, problems. A hybrid parallel update scheme concerning the stochastic input-output behaviour of each unit is presented. This parallel update scheme maintains the solution quality of the Boltzmann Machine optimizer, which is inherently sequential. Experimental results on the Maximum Independent Set problem demonstrate the benefit of using the proposed optimizer in terms of computation time. Excellent speedup has been obtained through parallel implementation on both shared memory and distributed memory architecures. |
en |
heal.publisher |
GORDON BREACH SCI PUBL LTD |
en |
heal.journalName |
International Journal of Computer Mathematics |
en |
dc.identifier.doi |
10.1080/00207169808804661 |
en |
dc.identifier.isi |
ISI:000072536500015 |
en |
dc.identifier.volume |
67 |
en |
dc.identifier.issue |
1-2 |
en |
dc.identifier.spage |
223 |
en |
dc.identifier.epage |
237 |
en |