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Refinement and property checking in high-level synthesis using attribute grammars

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dc.contributor.author Economakos, G en
dc.contributor.author Papakonstantinou, G en
dc.date.accessioned 2014-03-01T01:15:07Z
dc.date.available 2014-03-01T01:15:07Z
dc.date.issued 1999 en
dc.identifier.issn 0302-9743 en
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/13352
dc.subject Attribute Grammar en
dc.subject Compiler Construction en
dc.subject Digital Design en
dc.subject Hardware Design en
dc.subject Hardware Verification en
dc.subject High Level Synthesis en
dc.subject Levels of Abstraction en
dc.subject.classification Computer Science, Theory & Methods en
dc.title Refinement and property checking in high-level synthesis using attribute grammars en
heal.type journalArticle en
heal.identifier.primary 10.1007/3-540-48153-2_27 en
heal.identifier.secondary http://dx.doi.org/10.1007/3-540-48153-2_27 en
heal.language English en
heal.publicationDate 1999 en
heal.abstract Recent advances in fabrication technology have pushed the digital designers' perspective towards higher levels of abstraction. Previous work has shown that attribute grammars, used in traditional compiler construction, can also be effectively adopted to describe in a formal and uniform way high-level hardware compilation heuristics, their main advantages being modularity and declarative notation. In this paper, a more abstract form of attribute grammars, relational attribute grammars, are further applied as a framework over which formal hardware verification is performed along with synthesis. The overall hardware design methodology proposed is a novel idea that supports provable correct designs. en
heal.publisher SPRINGER-VERLAG BERLIN en
heal.journalName CORRECT HARDWARE DESIGN AND VERIFICATION METHODS en
heal.bookName LECTURE NOTES IN COMPUTER SCIENCE en
dc.identifier.doi 10.1007/3-540-48153-2_27 en
dc.identifier.isi ISI:000088608500027 en
dc.identifier.volume 1703 en
dc.identifier.spage 330 en
dc.identifier.epage 333 en


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