Chain grouping: A method for partitioning loops onto mesh-connected processor arrays

Tsanakas, P; Koziris, N; Papakonstantinou, G

dc.contributor.author	Tsanakas, P	en
dc.contributor.author	Koziris, N	en
dc.contributor.author	Papakonstantinou, G	en
dc.date.accessioned	2014-03-01T01:15:30Z
dc.date.available	2014-03-01T01:15:30Z
dc.date.issued	2000	en
dc.identifier.issn	1045-9219	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/13545
dc.subject	loop grouping	en
dc.subject	orthogonal projection	en
dc.subject	hyperplane method	en
dc.subject	uniform chains of iterations	en
dc.subject	mesh-connected architectures	en
dc.subject.classification	Computer Science, Theory & Methods	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	UNIFORM DEPENDENCIES	en
dc.subject.other	NESTED LOOPS	en
dc.subject.other	TRANSFORMATION	en
dc.subject.other	MULTICOMPUTERS	en
dc.subject.other	ALGORITHMS	en
dc.subject.other	TIME	en
dc.title	Chain grouping: A method for partitioning loops onto mesh-connected processor arrays	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/71.879777	en
heal.identifier.secondary	http://dx.doi.org/10.1109/71.879777	en
heal.language	English	en
heal.publicationDate	2000	en
heal.abstract	This paper presents Chain Grouping, a new low complexity method for the problem of partitioning the loop iteration space into groups with little intercommunication requirements, for mapping onto mesh-connected architectures. First, the iterations are scheduled in time, according to the hyperplane method, taking into consideration the minimum time displacement. Then, the iteration space is divided into discrete groups of related iterations, which are assigned to different processors, while preserving the optimal completion time. Chain Grouping is based on clustering together neighboring uniform chains of iterations, formed by a particular dependence vector. This vector will be proven as the best among all to reduce the total communication requirements. Inside every group, the optimal hyperplane scheduling is preserved and references to intragroup iterations are considerably increased. The partitioned groups are afterward assigned to meshes of processors. The resulting space mapping maximizes processor utilization and cuts down overall communication delays while preserving the optimal hyperplane time schedule.	en
heal.publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC	en
heal.journalName	IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS	en
dc.identifier.doi	10.1109/71.879777	en
dc.identifier.isi	ISI:000090137100007	en
dc.identifier.volume	11	en
dc.identifier.issue	9	en
dc.identifier.spage	941	en
dc.identifier.epage	955	en