dc.contributor.author |
Pekmestzi, KZ |
en |
dc.contributor.author |
Kalivas, P |
en |
dc.date.accessioned |
2014-03-01T01:15:31Z |
|
dc.date.available |
2014-03-01T01:15:31Z |
|
dc.date.issued |
2000 |
en |
dc.identifier.issn |
0922-5773 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/13563 |
|
dc.subject |
constant number multiplication |
en |
dc.subject |
serial multipliers |
en |
dc.subject |
systolic circuits |
en |
dc.subject |
canonic signed digit representation |
en |
dc.subject.classification |
Computer Science, Information Systems |
en |
dc.subject.classification |
Engineering, Electrical & Electronic |
en |
dc.title |
Constant number serial pipeline multipliers |
en |
heal.type |
journalArticle |
en |
heal.identifier.primary |
10.1023/A:1026507617721 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1023/A:1026507617721 |
en |
heal.language |
English |
en |
heal.publicationDate |
2000 |
en |
heal.abstract |
The pipeline form of the serial/parallel multiplier for constant numbers, which operates without insertion of zero words between successive data, is presented. The constant number is in Canonical Signed Digit (CSD) form and the other factor in two's complement form. The CSD form was chosen because it yields significant hardware reduction. Also, for the above data forms the Lyon's serial pipeline multiplier is examined. For these designs, a special algorithm for the multiplication of two's complement numbers with constant numbers in CSD representation was developed. The proposed serial pipeline multipliers are compared with the existing schemes from the point of hardware complexity. |
en |
heal.publisher |
KLUWER ACADEMIC PUBL |
en |
heal.journalName |
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY |
en |
dc.identifier.doi |
10.1023/A:1026507617721 |
en |
dc.identifier.isi |
ISI:000165811400004 |
en |
dc.identifier.volume |
26 |
en |
dc.identifier.issue |
3 |
en |
dc.identifier.spage |
361 |
en |
dc.identifier.epage |
368 |
en |