A bit-interleaved systolic architecture for a high-speed RSA system

Pekmestzi, KZ; Moshopoulos, NK

dc.contributor.author	Pekmestzi, KZ	en
dc.contributor.author	Moshopoulos, NK	en
dc.date.accessioned	2014-03-01T01:15:58Z
dc.date.available	2014-03-01T01:15:58Z
dc.date.issued	2001	en
dc.identifier.issn	0167-9260	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/13861
dc.subject	Montgomery	en
dc.subject	RSA	en
dc.subject	Square and multiply	en
dc.subject	Systolic circuit	en
dc.subject.classification	Computer Science, Hardware & Architecture	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Algorithms	en
dc.subject.other	Computer hardware	en
dc.subject.other	Multiplying circuits	en
dc.subject.other	Systolic circuits	en
dc.subject.other	Logic circuits	en
dc.title	A bit-interleaved systolic architecture for a high-speed RSA system	en
heal.type	journalArticle	en
heal.identifier.primary	10.1016/S0167-9260(01)00017-7	en
heal.identifier.secondary	http://dx.doi.org/10.1016/S0167-9260(01)00017-7	en
heal.language	English	en
heal.publicationDate	2001	en
heal.abstract	A new systolic serial-parallel scheme that implements the Montgomery multiplier is presented. The serial input of this multiplier consists of two sets of data that enter in a bit-interleaved form. The results are also derived in the same form. The design, with minor modifications, can be used for the implementation of the RSA algorithm by realizing the square-and-multiply algorithm. The circuit yields the lowest hardware complexity reported and permits high-speed operation with 100% efficiency. (C) 2001 Elsevier Science B.V. All rights reserved.	en
heal.publisher	ELSEVIER SCIENCE BV	en
heal.journalName	Integration, the VLSI Journal	en
dc.identifier.doi	10.1016/S0167-9260(01)00017-7	en
dc.identifier.isi	ISI:000172016100005	en
dc.identifier.volume	30	en
dc.identifier.issue	2	en
dc.identifier.spage	169	en
dc.identifier.epage	175	en