A parallel VLSI video/communication controller

Doumenis, G; Konstantoulakis, G; Korinthios, G; Lykakis, G; Reisis, D; Synnefakis, G

dc.contributor.author	Doumenis, G	en
dc.contributor.author	Konstantoulakis, G	en
dc.contributor.author	Korinthios, G	en
dc.contributor.author	Lykakis, G	en
dc.contributor.author	Reisis, D	en
dc.contributor.author	Synnefakis, G	en
dc.date.accessioned	2014-03-01T01:16:02Z
dc.date.available	2014-03-01T01:16:02Z
dc.date.issued	2001	en
dc.identifier.issn	0922-5773	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/13894
dc.subject	Interconnection networks	en
dc.subject	Packet networks	en
dc.subject	Parallel architectures	en
dc.subject	Shared memory	en
dc.subject	Traffic shaping	en
dc.subject	Video communication	en
dc.subject.classification	Computer Science, Information Systems	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Buffer storage	en
dc.subject.other	Interconnection networks	en
dc.subject.other	Multiplexing	en
dc.subject.other	Packet networks	en
dc.subject.other	Parallel processing systems	en
dc.subject.other	Real time systems	en
dc.subject.other	Video signal processing	en
dc.subject.other	VLSI circuits	en
dc.subject.other	Parallel architectures	en
dc.subject.other	Shared memory	en
dc.subject.other	Traffic shaping	en
dc.subject.other	Video communication	en
dc.subject.other	Visual communication	en
dc.title	A parallel VLSI video/communication controller	en
heal.type	journalArticle	en
heal.identifier.primary	10.1023/A:1011121709723	en
heal.identifier.secondary	http://dx.doi.org/10.1023/A:1011121709723	en
heal.language	English	en
heal.publicationDate	2001	en
heal.abstract	This paper presents a VLSI architecture specifically designed as a video/communication controller to support emerging applications in the area of video/data communications. The controller is a parallel architecture consisting of three (3) processing modules, a shared memory with four (4) banks and two (2) input/output modules and operating at the transfer speed of 622 Mbits/sec. The processing modules and memory banks communicate through a low cost interconnection scheme able though to perform at system's required data transfer rate. The entire system constitutes a component which can accommodate a switching system as an intelligent buffer with real time processing and multiplexing capabilities. The component performs operations on fixed and/or variable length packets of data on a stream basis. The architecture embeds both the processing and the memory modules, thus producing a ""system on a chip"" solution.	en
heal.publisher	KLUWER ACADEMIC PUBL	en
heal.journalName	Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology	en
dc.identifier.doi	10.1023/A:1011121709723	en
dc.identifier.isi	ISI:000168888000007	en
dc.identifier.volume	28	en
dc.identifier.issue	3	en
dc.identifier.spage	245	en
dc.identifier.epage	257	en