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A transceiver circuit for ATM networks

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dc.contributor.author Koukos, AK en
dc.contributor.author Kamaras, JG en
dc.contributor.author Evagelatos, AF en
dc.date.accessioned 2014-03-01T01:16:05Z
dc.date.available 2014-03-01T01:16:05Z
dc.date.issued 2001 en
dc.identifier.issn 0020-7217 en
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/13910
dc.subject.classification Engineering, Electrical & Electronic en
dc.title A transceiver circuit for ATM networks en
heal.type journalArticle en
heal.identifier.primary 10.1080/00207210110058157 en
heal.identifier.secondary http://dx.doi.org/10.1080/00207210110058157 en
heal.language English en
heal.publicationDate 2001 en
heal.abstract This paper presents a transceiver digital circuit. The circuit is responsible for the emission of packets to the asynchronous transfer mode (ATM) network as well as for the manipulation of received ATM packets belonging to virtual connections. It has been designed to support data communication services. The circuit, which can be used in terminals or in interworking units and switches, implements basic functions of the lower layers of the ATM protocol reference model. The transmission functionality includes cell buffering, header error control, cell assembling, rate coupling and information insertion. The receiver realizes information extraction, rate decoupling, cell buffering, header error detection and correction, connection identity fields extraction and identification, cell disassembling and classification, and idle cell discarding functions. The circuit has been implemented on applications specific integrated circuit (ASIC) chips. en
heal.publisher TAYLOR & FRANCIS LTD en
heal.journalName International Journal of Electronics en
dc.identifier.doi 10.1080/00207210110058157 en
dc.identifier.isi ISI:000170451900001 en
dc.identifier.volume 88 en
dc.identifier.issue 8 en
dc.identifier.spage 847 en
dc.identifier.epage 859 en


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