dc.contributor.author |
Pekmestzi, KZ |
en |
dc.contributor.author |
Kalivas, P |
en |
dc.contributor.author |
Moshopoulos, N |
en |
dc.date.accessioned |
2014-03-01T01:16:41Z |
|
dc.date.available |
2014-03-01T01:16:41Z |
|
dc.date.issued |
2001 |
en |
dc.identifier.issn |
1057-7130 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/14168 |
|
dc.subject |
Serial multiplier |
en |
dc.subject |
Serial squarer |
en |
dc.subject |
Systolic circuits |
en |
dc.subject.classification |
Engineering, Electrical & Electronic |
en |
dc.subject.other |
Adders |
en |
dc.subject.other |
Algorithms |
en |
dc.subject.other |
Binary sequences |
en |
dc.subject.other |
Shift registers |
en |
dc.subject.other |
Systolic arrays |
en |
dc.subject.other |
VLSI circuits |
en |
dc.subject.other |
Serial multiplier |
en |
dc.subject.other |
Serial squarer |
en |
dc.subject.other |
Systolic circuits |
en |
dc.subject.other |
Multiplying circuits |
en |
dc.title |
Long unsigned number systolic serial multipliers and squarers |
en |
heal.type |
journalArticle |
en |
heal.identifier.primary |
10.1109/82.924075 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1109/82.924075 |
en |
heal.language |
English |
en |
heal.publicationDate |
2001 |
en |
heal.abstract |
A systolic serial multiplier and a squarer for unsigned numbers - which operate without zero words inverted between successive data words, output the full product, and have only one clock cycle latency - are presented. The multiplier is based on a modified serial/parallel scheme that operates with 100% efficiency. The systolic form is obtained by merging two adjacent multiplier cells. The same technique is used for the design of a serial squarer. The systolisity and the continuous operation are achieved without an increase in hardware complexity. The proposed schemes are well suited for long number multiplication and squaring. |
en |
heal.publisher |
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
en |
heal.journalName |
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing |
en |
dc.identifier.doi |
10.1109/82.924075 |
en |
dc.identifier.isi |
ISI:000168916700011 |
en |
dc.identifier.volume |
48 |
en |
dc.identifier.issue |
3 |
en |
dc.identifier.spage |
316 |
en |
dc.identifier.epage |
321 |
en |