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Clock and data recovery circuit for 10-Gb/s asynchronous optical packets

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dc.contributor.author Kanellos, GT en
dc.contributor.author Stampoulidis, L en
dc.contributor.author Pleros, N en
dc.contributor.author Houbavlis, T en
dc.contributor.author Tsiokos, D en
dc.contributor.author Kehayas, E en
dc.contributor.author Avramopoulos, H en
dc.contributor.author Guekos, G en
dc.date.accessioned 2014-03-01T01:18:45Z
dc.date.available 2014-03-01T01:18:45Z
dc.date.issued 2003 en
dc.identifier.issn 1041-1135 en
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/15181
dc.subject Asynchronous traffic en
dc.subject Clock and data recovery (CDR) en
dc.subject Optical packet switching en
dc.subject Ultrafast nonlinear interferometer (UNI) en
dc.subject.classification Engineering, Electrical & Electronic en
dc.subject.classification Optics en
dc.subject.classification Physics, Applied en
dc.subject.other Data communication systems en
dc.subject.other Fabry-Perot interferometers en
dc.subject.other Light amplifiers en
dc.subject.other Optical filters en
dc.subject.other Optical switches en
dc.subject.other Packet switching en
dc.subject.other Telecommunication traffic en
dc.subject.other Asynchronous optical packets en
dc.subject.other Asynchronous traffic en
dc.subject.other Data recovery circuit en
dc.subject.other Optical clock en
dc.subject.other Ultrafast nonlinear interferometer en
dc.subject.other Integrated optoelectronics en
dc.title Clock and data recovery circuit for 10-Gb/s asynchronous optical packets en
heal.type journalArticle en
heal.identifier.primary 10.1109/LPT.2003.818647 en
heal.identifier.secondary http://dx.doi.org/10.1109/LPT.2003.818647 en
heal.language English en
heal.publicationDate 2003 en
heal.abstract We demonstrate an all-optical clock and data recovery circuit for short asynchronous data packets at 10-Gb/s line rate. The technique employs a Fabry-Pérot filter and an ultrafast nonlinear interferometer (UNI) to generate the local packet clock, followed by a second UNI gate to act as decision element, performing a logical and operation between the extracted clocks and the incoming data packets. The circuit can handle short packets arriving at time intervals as short as 1.5 ns and arbitrary phase alignment. en
heal.publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC en
heal.journalName IEEE Photonics Technology Letters en
dc.identifier.doi 10.1109/LPT.2003.818647 en
dc.identifier.isi ISI:000186113900058 en
dc.identifier.volume 15 en
dc.identifier.issue 11 en
dc.identifier.spage 1666 en
dc.identifier.epage 1668 en


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