10-Gb/s All-Optical Half-Adder with Interferometric SOA Gates

Tsiokos, D; Kehayas, E; Vyrsokinos, K; Houbavlis, T; Stampoulidis, L; Kanellos, GT; Pleros, N; Guekos, G; Avramopoulos, H

dc.contributor.author	Tsiokos, D	en
dc.contributor.author	Kehayas, E	en
dc.contributor.author	Vyrsokinos, K	en
dc.contributor.author	Houbavlis, T	en
dc.contributor.author	Stampoulidis, L	en
dc.contributor.author	Kanellos, GT	en
dc.contributor.author	Pleros, N	en
dc.contributor.author	Guekos, G	en
dc.contributor.author	Avramopoulos, H	en
dc.date.accessioned	2014-03-01T01:19:42Z
dc.date.available	2014-03-01T01:19:42Z
dc.date.issued	2004	en
dc.identifier.issn	1041-1135	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/15675
dc.subject	Half-adder	en
dc.subject	High-speed optical logic	en
dc.subject	Optical gate	en
dc.subject	Optical signal processing	en
dc.subject	Ultrafast nonlinear interferometer (UNI)	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.classification	Optics	en
dc.subject.classification	Physics, Applied	en
dc.subject.other	Interferometers	en
dc.subject.other	Optical fibers	en
dc.subject.other	Optical switches	en
dc.subject.other	Optimization	en
dc.subject.other	Phase modulation	en
dc.subject.other	Polarization	en
dc.subject.other	Signal processing	en
dc.subject.other	Transistors	en
dc.subject.other	Optical gates	en
dc.subject.other	Ultrafast nonlinear interferometers (UNI)	en
dc.subject.other	Adders	en
dc.title	10-Gb/s All-Optical Half-Adder with Interferometric SOA Gates	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/LPT.2003.819394	en
heal.identifier.secondary	http://dx.doi.org/10.1109/LPT.2003.819394	en
heal.language	English	en
heal.publicationDate	2004	en
heal.abstract	In this letter, we report an all-optical module that generates simultaneously four Boolean operations at 10 Gb/s. The circuit employs two cascaded ultrafast nonlinear interferometers and requires only two signals as inputs. The first gate is configured as a 2 × 2 exchange-bypass switch and provides OR and AND logical operations. The second gate generates XOR (SUM bit) and AND (CARRY bit) Boolean operations and constitutes a binary half-adder. Successful operation of the system is demonstrated with 10-Gb/s return-to-zero pseudorandom data patterns.	en
heal.publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC	en
heal.journalName	IEEE Photonics Technology Letters	en
dc.identifier.doi	10.1109/LPT.2003.819394	en
dc.identifier.isi	ISI:000187885800095	en
dc.identifier.volume	16	en
dc.identifier.issue	1	en
dc.identifier.spage	284	en
dc.identifier.epage	286	en