dc.contributor.author |
Kalivas, P |
en |
dc.contributor.author |
Vassilakis, V |
en |
dc.contributor.author |
Meletis, C |
en |
dc.contributor.author |
Pekmestzi, KZ |
en |
dc.date.accessioned |
2014-03-01T01:21:45Z |
|
dc.date.available |
2014-03-01T01:21:45Z |
|
dc.date.issued |
2005 |
en |
dc.identifier.issn |
0922-5773 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/16353 |
|
dc.subject |
Array multipliers |
en |
dc.subject |
FIR filters |
en |
dc.subject.classification |
Computer Science, Information Systems |
en |
dc.subject.classification |
Engineering, Electrical & Electronic |
en |
dc.subject.other |
Adders |
en |
dc.subject.other |
Arrays |
en |
dc.subject.other |
Computational complexity |
en |
dc.subject.other |
Computer architecture |
en |
dc.subject.other |
Computer hardware |
en |
dc.subject.other |
Data reduction |
en |
dc.subject.other |
Parallel processing systems |
en |
dc.subject.other |
Vectors |
en |
dc.subject.other |
Array multipliers |
en |
dc.subject.other |
Clock cycles |
en |
dc.subject.other |
FIR filter schemes |
en |
dc.subject.other |
Full-adders |
en |
dc.subject.other |
FIR filters |
en |
dc.title |
A new low latency parallel FIR filter scheme |
en |
heal.type |
journalArticle |
en |
heal.identifier.primary |
10.1007/s11265-005-4847-4 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1007/s11265-005-4847-4 |
en |
heal.language |
English |
en |
heal.publicationDate |
2005 |
en |
heal.abstract |
A new array type parallel scheme for an FIR digital filter is presented in this paper. The proposed scheme is based on the structure of the carry-save array multiplier where each cell implements the computation of an FIR filter at the bit-level. This structure leads to latency independent of the number of the filter taps. The proposed scheme is pipelined at the bit-level is systolic at the cell-level and requires less hardware than other schemes based on discrete multipliers. © 2005 Springer Science + Business Media Inc. |
en |
heal.publisher |
SPRINGER |
en |
heal.journalName |
Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology |
en |
dc.identifier.doi |
10.1007/s11265-005-4847-4 |
en |
dc.identifier.isi |
ISI:000227184300008 |
en |
dc.identifier.volume |
39 |
en |
dc.identifier.issue |
3 |
en |
dc.identifier.spage |
313 |
en |
dc.identifier.epage |
322 |
en |