Pipelined array-based FIR filter folding

Bougas, P; Kalivas, P; Tsirikos, A; Pekmestzi, KZ

dc.contributor.author	Bougas, P	en
dc.contributor.author	Kalivas, P	en
dc.contributor.author	Tsirikos, A	en
dc.contributor.author	Pekmestzi, KZ	en
dc.date.accessioned	2014-03-01T01:22:56Z
dc.date.available	2014-03-01T01:22:56Z
dc.date.issued	2005	en
dc.identifier.issn	1057-7122	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/16731
dc.subject	Digital filters	en
dc.subject	Multiplying circuits	en
dc.subject	Systolic arrays	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Computational complexity	en
dc.subject.other	Computer simulation	en
dc.subject.other	Digital signal processing	en
dc.subject.other	Multiplying circuits	en
dc.subject.other	Systolic arrays	en
dc.subject.other	Hardware complexity	en
dc.subject.other	Pipelined multiple arrays	en
dc.subject.other	FIR filters	en
dc.title	Pipelined array-based FIR filter folding	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/TCSI.2004.838542	en
heal.identifier.secondary	http://dx.doi.org/10.1109/TCSI.2004.838542	en
heal.language	English	en
heal.publicationDate	2005	en
heal.abstract	The elaborate design of folded finite-impulse response (FIR) filters based on pipelined multiplier arrays is presented in this paper. The design is considered at the bit-level and the internal delays of the pipelined multiplier array are fully exploited in order to reduce hardware complexity. Both direct and transposed FIR filter forms are considered. The carry-save and the carry-propagate multiplier arrays are studied for the filter implementations. Partially folded architectures are also proposed which are implemented by cascading a number of folded FIR filters. The proposed schemes are compared as to the aspect of hardware complexity with a straightforward implementation of a folded FIR filter based on the pipelined Wallace Tree multiplier. The comparison reveals that the proposed schemes require 20%-30% less hardware. Finally, efficient implementation of partially folded FIR filter circuits is presented when constraints in area, power consumption and clock frequency are given. © 2005 IEEE.	en
heal.publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC	en
heal.journalName	IEEE Transactions on Circuits and Systems I: Regular Papers	en
dc.identifier.doi	10.1109/TCSI.2004.838542	en
dc.identifier.isi	ISI:000226247800011	en
dc.identifier.volume	52	en
dc.identifier.issue	1	en
dc.identifier.spage	108	en
dc.identifier.epage	118	en