A 1-V, 5.5-GHz, CMOS LNA with multiple magnetic feedback

Vitzilaios, G; Papananos, Y; Theodoratos, G; Vasilopoulos, A

dc.contributor.author	Vitzilaios, G	en
dc.contributor.author	Papananos, Y	en
dc.contributor.author	Theodoratos, G	en
dc.contributor.author	Vasilopoulos, A	en
dc.date.accessioned	2014-03-01T01:23:21Z
dc.date.available	2014-03-01T01:23:21Z
dc.date.issued	2006	en
dc.identifier.issn	1057-7130	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/16926
dc.subject	CMOS RF integrated circuit design	en
dc.subject	Integrated low-noise amplifier (LNA)	en
dc.subject	Integrated transformers	en
dc.subject	Low voltage	en
dc.subject	Magnetic feedback technique	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	CMOS integrated circuits	en
dc.subject.other	Electric network topology	en
dc.subject.other	Electric transformers	en
dc.subject.other	Feedback	en
dc.subject.other	Logic gates	en
dc.subject.other	Spurious signal noise	en
dc.subject.other	CMOS RF integrated circuit design	en
dc.subject.other	Integrated transformers	en
dc.subject.other	Magnetic feedback technique	en
dc.subject.other	Monolithic transformers	en
dc.subject.other	Low noise amplifiers	en
dc.title	A 1-V, 5.5-GHz, CMOS LNA with multiple magnetic feedback	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/TCSII.2006.881810	en
heal.identifier.secondary	http://dx.doi.org/10.1109/TCSII.2006.881810	en
heal.language	English	en
heal.publicationDate	2006	en
heal.abstract	A CMOS low-noise amplifier that utilizes multiple monolithic transformer magnetic feedback to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance is presented. The multiple transformer topology permits negative and positive feedback to be applied constructively, allowing for a stable design with adequate gain and large reverse isolation without noise figure (NF) degradation. Simulation results indicate voltage conversion gain of 17 dB, NF of 1.6 dB, and best-case third-order input intercept point of 13 dBm. The design is being implemented in a 0.13-μm CMOS technology. © 2006 IEEE.	en
heal.publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC	en
heal.journalName	IEEE Transactions on Circuits and Systems II: Express Briefs	en
dc.identifier.doi	10.1109/TCSII.2006.881810	en
dc.identifier.isi	ISI:000241006200036	en
dc.identifier.volume	53	en
dc.identifier.issue	9	en
dc.identifier.spage	971	en
dc.identifier.epage	975	en