Packet clock recovery using a bismuth oxide fiber-based optical power limiter

Kouloumentas, Ch; Pleros, N; Zakynthinos, P; Petrantonakis, D; Apostolopoulos, D; Zouraraki, O; Tzanakaki, A; Avramopoulos, H; Tomkos, I

dc.contributor.author	Kouloumentas, Ch	en
dc.contributor.author	Pleros, N	en
dc.contributor.author	Zakynthinos, P	en
dc.contributor.author	Petrantonakis, D	en
dc.contributor.author	Apostolopoulos, D	en
dc.contributor.author	Zouraraki, O	en
dc.contributor.author	Tzanakaki, A	en
dc.contributor.author	Avramopoulos, H	en
dc.contributor.author	Tomkos, I	en
dc.date.accessioned	2014-03-01T01:26:51Z
dc.date.available	2014-03-01T01:26:51Z
dc.date.issued	2007	en
dc.identifier.issn	1094-4087	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/18262
dc.subject	Clock Recovery	en
dc.subject.classification	Optics	en
dc.subject.other	Bismuth compounds	en
dc.subject.other	Limiters	en
dc.subject.other	Optical communication	en
dc.subject.other	Optical fibers	en
dc.subject.other	Power control	en
dc.subject.other	Data packets	en
dc.subject.other	Power limiting configuration	en
dc.subject.other	Packet switching	en
dc.title	Packet clock recovery using a bismuth oxide fiber-based optical power limiter	en
heal.type	journalArticle	en
heal.identifier.primary	10.1364/OE.15.009948	en
heal.identifier.secondary	http://dx.doi.org/10.1364/OE.15.009948	en
heal.language	English	en
heal.publicationDate	2007	en
heal.abstract	We demonstrate an optical clock recovery circuit that extracts the line rate component on a per packet basis from short data packets at 40 Gb/s. The circuit comprises a Fabry-Perot filter followed by a novel power limiting configuration, which in turn consists of a 5m highly nonlinear bismuth oxide fiber in cascade with an optical bandpass filter. Both experimental and simulation-based results are in close agreement and reveal that the proposed circuit acquires the timing information within only a small number of bits, yielding a packet clock for every respective data packet. Moreover, we investigate theoretically the scaling laws for the parameters of the circuit for operation beyond 40 Gb/s and present simulation results showing successful packet clock extraction for 160 Gb/s data packets. Finally, the circuit's potential for operation at 320 Gb/s is discussed, indicating that ultrafast packet clock recovery should be in principle feasible by exploiting the passive structure of the device and the fsec-scale nonlinear response of the optical fiber. (C) 2007 Optical Society of America.	en
heal.publisher	OPTICAL SOC AMER	en
heal.journalName	Optics Express	en
dc.identifier.doi	10.1364/OE.15.009948	en
dc.identifier.isi	ISI:000248753100006	en
dc.identifier.volume	15	en
dc.identifier.issue	16	en
dc.identifier.spage	9948	en
dc.identifier.epage	9953	en