A power-aware placement and routing algorithm targeting 3D FPGAs

Siozios, K; Soudris, D

dc.contributor.author	Siozios, K	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T01:27:47Z
dc.date.available	2014-03-01T01:27:47Z
dc.date.issued	2008	en
dc.identifier.issn	15461998	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/18569
dc.subject	3D FPGA	en
dc.subject	Algorithm	en
dc.subject	CAD Tool	en
dc.subject	Place	en
dc.subject	Power Management	en
dc.subject	Route	en
dc.subject.other	3D FPGA	en
dc.subject.other	CAD Tool	en
dc.subject.other	Place	en
dc.subject.other	Power Management	en
dc.subject.other	Route	en
dc.subject.other	Computer aided design	en
dc.subject.other	DC generators	en
dc.subject.other	Electric power measurement	en
dc.subject.other	Electric power utilization	en
dc.subject.other	Energy management	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	Three dimensional	en
dc.subject.other	Routing algorithms	en
dc.title	A power-aware placement and routing algorithm targeting 3D FPGAs	en
heal.type	journalArticle	en
heal.identifier.primary	10.1166/jolpe.2008.184	en
heal.identifier.secondary	http://dx.doi.org/10.1166/jolpe.2008.184	en
heal.publicationDate	2008	en
heal.abstract	In current reconfigurable architectures, the interconnect structures increasingly contribute to the delay and power consumption budget. The demand for increased clock frequencies and logic availability (smaller area foot print) makes the problem even more important, leading among others to rapid elevation in power density. Three-dimensional (3D) architectures are able to alleviate this problem by accommodating a number of functional layers, each of which might be fabricated in different technology. Since power consumption is a critical challenge for implementing applications onto reconfigurable hardware, a novel power-aware placement and routing (P&R) algorithm targeting to 3D FPGAs, is introduced. The proposed algorithm achieves to redistribute the switched capacitance over identical hardware resources in a rather ""balanced"" profile, reducing among others the number of hotspot regions, the maximal values of power sources at hotspots, as well as the percentage of device area that consumes high power. For evaluation purposes, the proposed approach is realized as a new CAD tool, named 3DPR0 (3D-Placement-and-Routing-Optimization), which is part of the complete framework, named 3D MEANDER. Comparing to alternative solutions, the proposed one reduces the percentage of silicon area that operates under high power by 63%, while it leads to energy savings (about 9%), with an almost negligible penalty in application's delay ranging from 1% up to 5%. Copyright © 2008 American Scientific Publishers.	en
heal.journalName	Journal of Low Power Electronics	en
dc.identifier.doi	10.1166/jolpe.2008.184	en
dc.identifier.volume	4	en
dc.identifier.issue	3	en
dc.identifier.spage	275	en
dc.identifier.epage	289	en