3-D technology assessment: Path-finding the technology/design sweet-spot

Marchal, P; Bougard, B; Katti, G; Stucchi, M; Dehaene, W; Papanikolaou, A; Verkest, D; Swinnen, B; Beyne, E

dc.contributor.author	Marchal, P	en
dc.contributor.author	Bougard, B	en
dc.contributor.author	Katti, G	en
dc.contributor.author	Stucchi, M	en
dc.contributor.author	Dehaene, W	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Verkest, D	en
dc.contributor.author	Swinnen, B	en
dc.contributor.author	Beyne, E	en
dc.date.accessioned	2014-03-01T01:29:29Z
dc.date.available	2014-03-01T01:29:29Z
dc.date.issued	2009	en
dc.identifier.issn	00189219	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/19280
dc.subject	Design automation	en
dc.subject	Design centering	en
dc.subject	Integrated circuit design	en
dc.subject	Technology assessment	en
dc.subject.other	Computer aided design	en
dc.subject.other	Integrated circuit manufacture	en
dc.subject.other	Integrated circuits	en
dc.subject.other	Semiconducting indium	en
dc.subject.other	Semiconductor device manufacture	en
dc.subject.other	Strategic planning	en
dc.subject.other	Technological forecasting	en
dc.subject.other	Three dimensional	en
dc.subject.other	Design automation	en
dc.subject.other	Design centering	en
dc.subject.other	Design options	en
dc.subject.other	Design strategies	en
dc.subject.other	Holistic approaches	en
dc.subject.other	Integrated circuit design	en
dc.subject.other	Moore's laws	en
dc.subject.other	Path findings	en
dc.subject.other	Road maps	en
dc.subject.other	Semiconductor industries	en
dc.subject.other	System designs	en
dc.subject.other	Technology assessment	en
dc.subject.other	Technology development	en
dc.subject.other	Technology options	en
dc.subject.other	Test strategies	en
dc.subject.other	Technology	en
dc.title	3-D technology assessment: Path-finding the technology/design sweet-spot	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/JPROC.2008.2007471	en
heal.identifier.secondary	http://dx.doi.org/10.1109/JPROC.2008.2007471	en
heal.identifier.secondary	4796274	en
heal.publicationDate	2009	en
heal.abstract	It is widely acknowledged that three-dimensional (3-D) technologies offer numerous opportunities for system design. In recent years, significant progress has been made on these 3-D technologies, and they have become probably the best hope for carrying the semiconductor industry beyond the path of Moore's law. However, a clear roadmap is missing to successfully introduce this 3-D technology onto the market. Today, a plurality of 3-D technology options exists, which requires different design and test strategies. To crystallize the many technology options in a few mainstream technologies, it is mandatory to coexplore both technology and design options. The contribution of this paper is to introduce a novel path finding methodology to untangle the many intertwined design/technology options. This holistic approach will be applied on a representative 3-D case study. Initial results demonstrate the benefits of the proposed path-finding methodology to steer the technology development and fine-tune design strategies. © 2006 IEEE.	en
heal.journalName	Proceedings of the IEEE	en
dc.identifier.doi	10.1109/JPROC.2008.2007471	en
dc.identifier.volume	97	en
dc.identifier.issue	1	en
dc.identifier.spage	96	en
dc.identifier.epage	107	en