Designing a novel high-performance FPGA architecture for data intensive applications

Siozios, K; Soudris, D

dc.contributor.author	Siozios, K	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T01:30:08Z
dc.date.available	2014-03-01T01:30:08Z
dc.date.issued	2009	en
dc.identifier.issn	1861-8200	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/19480
dc.subject	CAD tool	en
dc.subject	FPGA architecture	en
dc.subject	Heterogeneous interconnection architecture	en
dc.subject	High-performance	en
dc.subject	Switch Box	en
dc.subject.other	CAD tool	en
dc.subject.other	FPGA architecture	en
dc.subject.other	Heterogeneous interconnection architecture	en
dc.subject.other	High-performance	en
dc.subject.other	Switch Box	en
dc.subject.other	Applications	en
dc.subject.other	Architecture	en
dc.subject.other	Computer aided design	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	Software architecture	en
dc.subject.other	Timing circuits	en
dc.subject.other	Architectural design	en
dc.title	Designing a novel high-performance FPGA architecture for data intensive applications	en
heal.type	journalArticle	en
heal.identifier.primary	10.1007/s11554-008-0099-4	en
heal.identifier.secondary	http://dx.doi.org/10.1007/s11554-008-0099-4	en
heal.language	English	en
heal.publicationDate	2009	en
heal.abstract	A wide variety of real-time applications (e.g. multimedia, communication, etc.) require implementations that meet tight timing constraints. This work introduces novel high-performance FPGA architecture capable of implementing efficiently any time critical application. The fundamental contribution of the proposed reconfigurable architecture is the design of a highly efficient (performance and power consumption) interconnection structure, taking into consideration the statistical and spatial data extracted from applications, which are implemented on Virtex FPGAs. The derived architecture is software-supported by the MEANDER design framework. Using a number of real-time applications, extensive comparison study in terms of several design parameters proves the effectiveness of the proposed architecture against to Virtex one. More specifically, the proposed architecture achieves performance improvement and power savings up to 20 and 16%, respectively. Moreover, compared to a Virtex architecture with same power budget, our architecture achieves performance improvement by 42%. © 2008 Springer-Verlag.	en
heal.publisher	SPRINGER HEIDELBERG	en
heal.journalName	Journal of Real-Time Image Processing	en
dc.identifier.doi	10.1007/s11554-008-0099-4	en
dc.identifier.isi	ISI:000283783200005	en
dc.identifier.volume	4	en
dc.identifier.issue	2	en
dc.identifier.spage	155	en
dc.identifier.epage	166	en