Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths

Xydis, S; Economakos, G; Pekmestzi, K

dc.contributor.author	Xydis, S	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T01:30:08Z
dc.date.available	2014-03-01T01:30:08Z
dc.date.issued	2009	en
dc.identifier.issn	0167-9260	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/19482
dc.subject	Array multiplier	en
dc.subject	Canonical interconnection	en
dc.subject	Carry-save arithmetic	en
dc.subject	Chain addition	en
dc.subject	Coarse-grain reconfigurable architectures	en
dc.subject	Flexibility inlining	en
dc.subject.classification	Computer Science, Hardware & Architecture	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Array multiplier	en
dc.subject.other	Canonical interconnection	en
dc.subject.other	Carry-save arithmetic	en
dc.subject.other	Coarse-grain reconfigurable architectures	en
dc.subject.other	Flexibility inlining	en
dc.subject.other	Frequency multiplying circuits	en
dc.subject.other	Signal processing	en
dc.subject.other	Digital signal processing	en
dc.title	Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths	en
heal.type	journalArticle	en
heal.identifier.primary	10.1016/j.vlsi.2008.12.003	en
heal.identifier.secondary	http://dx.doi.org/10.1016/j.vlsi.2008.12.003	en
heal.language	English	en
heal.publicationDate	2009	en
heal.abstract	This paper introduces a design technique for coarse-grained reconfigurable architectures targeting digital signal processing (DSP) applications. The design procedure is analyzed in detail and an area-time-power efficient reconfigurable kernel architecture is presented. The proposed technique inlines flexibility into custom carry-save (CS) arithmetic datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a transformation, called uniformity transformation, imposed on the basic architectures of CS-multipliers and CS-chain-adders/subtractors. Experimental results including quantitative and qualitative comparisons with existing reconfigurable arithmetic cores and exploration results of the proposed reconfigurable architecture are provided. (C) 2009 Elsevier B.V. All rights reserved.	en
heal.publisher	ELSEVIER SCIENCE BV	en
heal.journalName	Integration, the VLSI Journal	en
dc.identifier.doi	10.1016/j.vlsi.2008.12.003	en
dc.identifier.isi	ISI:000269594600006	en
dc.identifier.volume	42	en
dc.identifier.issue	4	en
dc.identifier.spage	486	en
dc.identifier.epage	503	en