Efficient reconfigurable embedded parsers

Pavlatos, C; Dimopoulos, AC; Koulouris, A; Andronikos, T; Panagopoulos, I; Papakonstantinou, G

dc.contributor.author	Pavlatos, C	en
dc.contributor.author	Dimopoulos, AC	en
dc.contributor.author	Koulouris, A	en
dc.contributor.author	Andronikos, T	en
dc.contributor.author	Panagopoulos, I	en
dc.contributor.author	Papakonstantinou, G	en
dc.date.accessioned	2014-03-01T01:30:18Z
dc.date.available	2014-03-01T01:30:18Z
dc.date.issued	2009	en
dc.identifier.issn	1477-8424	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/19543
dc.subject	Context-free grammars	en
dc.subject	FPGA	en
dc.subject	Reconfigurable parsers	en
dc.subject	Syntactic pattern recognition	en
dc.subject.classification	Computer Science, Software Engineering	en
dc.subject.other	Combinatorial mathematics	en
dc.subject.other	Computational grammars	en
dc.subject.other	Context free grammars	en
dc.subject.other	Feature extraction	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	Hardware	en
dc.subject.other	Logic circuits	en
dc.subject.other	Object recognition	en
dc.subject.other	Pattern recognition	en
dc.subject.other	Syntactics	en
dc.subject.other	Automated syntheses	en
dc.subject.other	FPGA	en
dc.subject.other	Fundamental operations	en
dc.subject.other	Hardware architectures	en
dc.subject.other	Hardware designs	en
dc.subject.other	Hardware implementations	en
dc.subject.other	Highly efficient	en
dc.subject.other	Input strings	en
dc.subject.other	Orders of magnitudes	en
dc.subject.other	Parsing algorithms	en
dc.subject.other	Reconfigurable	en
dc.subject.other	Reconfigurable parsers	en
dc.subject.other	Software implementations	en
dc.subject.other	Source codes	en
dc.subject.other	Speed-up	en
dc.subject.other	Syntactic pattern recognition	en
dc.subject.other	Time complexities	en
dc.subject.other	Xilinx fpga	en
dc.subject.other	Computer hardware description languages	en
dc.title	Efficient reconfigurable embedded parsers	en
heal.type	journalArticle	en
heal.identifier.primary	10.1016/j.cl.2007.08.001	en
heal.identifier.secondary	http://dx.doi.org/10.1016/j.cl.2007.08.001	en
heal.language	English	en
heal.publicationDate	2009	en
heal.abstract	This paper presents a highly efficient architecture for the hardware implementation of context-free grammar (CFG) parsers. Its efficiency stems from an innovative combinatorial circuit that implements the fundamental operation of Earley's parsing algorithm in time complexity O(log(2)vertical bar G vertical bar). where vertical bar G vertical bar is the size of the CFG. Using this hardware architecture in a template form. we have developed an automated synthesis tool that, given the specification of an arbitrary CFG. generates the HDL (Hardware Design Language) synthesizable source code of the hardware parser for the given grammar. The generated source has been simulated for validation, synthesized and tested on a Xilinx FPGA (Field Programmable Gate Array) board. Our method increases the performance by a factor of one to two orders of magnitude, compared to previous hardware implementations. depending on the size of the grammar and the input string length. The speedup. compared to the pure software implementation. varies from two orders of magnitude for toy-scale grammars to six orders of magnitude for large real life grammars. This makes it particularly appealing for applications where (syntactic) pattern recognition response is a crucial aspect. (C) 2007 Elsevier Ltd. All rights reserved.	en
heal.publisher	PERGAMON-ELSEVIER SCIENCE LTD	en
heal.journalName	Computer Languages, Systems and Structures	en
dc.identifier.doi	10.1016/j.cl.2007.08.001	en
dc.identifier.isi	ISI:000262973600004	en
dc.identifier.volume	35	en
dc.identifier.issue	2	en
dc.identifier.spage	196	en
dc.identifier.epage	215	en