Extending an embedded RISC microprocessor for efficient translation based Java execution

Sideris, I; Pekmestzi, K; Economakos, G

dc.contributor.author	Sideris, I	en
dc.contributor.author	Pekmestzi, K	en
dc.contributor.author	Economakos, G	en
dc.date.accessioned	2014-03-01T01:30:29Z
dc.date.available	2014-03-01T01:30:29Z
dc.date.issued	2009	en
dc.identifier.issn	0141-9331	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/19601
dc.subject	Codesigned virtual machine	en
dc.subject	Embedded Java	en
dc.subject	Java processor	en
dc.subject.classification	Computer Science, Hardware & Architecture	en
dc.subject.classification	Computer Science, Theory & Methods	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Codesigned virtual machine	en
dc.subject.other	Embedded appliances	en
dc.subject.other	Embedded Java	en
dc.subject.other	Embedded RISC processors	en
dc.subject.other	Hand held device	en
dc.subject.other	Java execution	en
dc.subject.other	Java processor	en
dc.subject.other	Java virtual machines	en
dc.subject.other	Operating systems	en
dc.subject.other	Risc microprocessors	en
dc.subject.other	RISC processors	en
dc.subject.other	Security checks	en
dc.subject.other	Set top box	en
dc.subject.other	Smart phones	en
dc.subject.other	Computer operating systems	en
dc.subject.other	Embedded systems	en
dc.subject.other	Java programming language	en
dc.subject.other	Reduced instruction set computing	en
dc.title	Extending an embedded RISC microprocessor for efficient translation based Java execution	en
heal.type	journalArticle	en
heal.identifier.primary	10.1016/j.micpro.2009.06.003	en
heal.identifier.secondary	http://dx.doi.org/10.1016/j.micpro.2009.06.003	en
heal.language	English	en
heal.publicationDate	2009	en
heal.abstract	Java has gained great popularity in embedded appliances such as set-top boxes, smart phones and other hand held devices. In this paper we propose a translation based hw/sw codesigned Java virtual machine architecture, which extends a typical embedded RISC processor. The architectural extensions we propose include special instructions that accelerate translated blocks dispatch and security checks for arrays and objects. The extensions are done in a way that operating systems support is maintained, something that makes their adoption more attractive. Benchmarking using Embedded Caffeine Mark (ECM) benchmarks, showed significant speedups, especially when high performance RISC processors are employed. (C) 2009 Elsevier B.V. All rights reserved.	en
heal.publisher	ELSEVIER SCIENCE BV	en
heal.journalName	Microprocessors and Microsystems	en
dc.identifier.doi	10.1016/j.micpro.2009.06.003	en
dc.identifier.isi	ISI:000272332600001	en
dc.identifier.volume	33	en
dc.identifier.issue	7-8	en
dc.identifier.spage	415	en
dc.identifier.epage	429	en