High-level estimation methodology for designing the instruction cache memory of programmable embedded platforms

Kroupis, N; Soudris, D

dc.contributor.author	Kroupis, N	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T01:30:51Z
dc.date.available	2014-03-01T01:30:51Z
dc.date.issued	2009	en
dc.identifier.issn	1751-8601	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/19650
dc.subject	Instruction Cache	en
dc.subject.classification	Computer Science, Hardware & Architecture	en
dc.subject.classification	Computer Science, Theory & Methods	en
dc.subject.other	Cache memory	en
dc.subject.other	Channel capacity	en
dc.subject.other	Computational complexity	en
dc.subject.other	Computer software	en
dc.subject.other	Digital signal processing	en
dc.subject.other	Digital signal processors	en
dc.subject.other	Embedded systems	en
dc.subject.other	Estimation	en
dc.subject.other	General purpose computers	en
dc.subject.other	Interconnection networks	en
dc.subject.other	Maximum likelihood estimation	en
dc.subject.other	Signal processing	en
dc.subject.other	Assembly codes	en
dc.subject.other	C codes	en
dc.subject.other	Cache parameters	en
dc.subject.other	Data intensives	en
dc.subject.other	Data-intensive applications	en
dc.subject.other	Design phasis	en
dc.subject.other	Different domains	en
dc.subject.other	Efficient designs	en
dc.subject.other	Embedded platforms	en
dc.subject.other	Embedded processors	en
dc.subject.other	Estimation methodologies	en
dc.subject.other	Estimation procedures	en
dc.subject.other	Executed instructions	en
dc.subject.other	General-purpose processors	en
dc.subject.other	High-level estimations	en
dc.subject.other	Instruction cache miss	en
dc.subject.other	Instruction caches	en
dc.subject.other	Low complexity	en
dc.subject.other	Miss rates	en
dc.subject.other	Modern applications	en
dc.subject.other	Orders of magnitudes	en
dc.subject.other	Real-life datum	en
dc.subject.other	Required time	en
dc.subject.other	Simulation-based	en
dc.subject.other	Software tools	en
dc.subject.other	Specific informations	en
dc.subject.other	Three stages	en
dc.subject.other	Time to markets	en
dc.subject.other	Time-consuming tasks	en
dc.subject.other	Typical designs	en
dc.subject.other	Applications	en
dc.title	High-level estimation methodology for designing the instruction cache memory of programmable embedded platforms	en
heal.type	journalArticle	en
heal.identifier.primary	10.1049/iet-cdt:20080009	en
heal.identifier.secondary	http://dx.doi.org/10.1049/iet-cdt:20080009	en
heal.language	English	en
heal.publicationDate	2009	en
heal.abstract	Considering the time-to-market restrictions and the increased computational complexity of modern applications, the efficient design of data intensive digital signal processing (DSP) applications is a challenging problem. A typical design exploration procedure, which uses simulation-based tools for various cache parameters, is a rather time-consuming task, even for low-complexity applications. The main goal is the introduction of a novel estimation methodology, which provides fast and accurate estimates of the number of executed instructions and the instruction cache miss rate of data intensive applications implemented on a programmable embedded platform, during the early design phases. The proposed methodology consists of three stages, where the first one is a platform-independent stage, whereas the remaining two use information from the chosen embedded platform. In particular, specific information is extracted from both the high-level code description (C code) of the application and its corresponding assembly code, without carrying out any kind of simulation. The proposed methodology requires only a single execution of the application in a general-purpose processor and uses only the assembly code of the targeted embedded processor. To accelerate the estimation procedure, a novel software tool, which implements the proposed methodology, has been developed. Using nine real-life data intensive applications from different domains of the DSP field, it has been proved that with the proposed methodology the number of instructions and the miss rate of the instruction cache can be estimated with very high accuracy (>90). Furthermore, the required time cost is much smaller (orders of magnitude) than the existing simulation-based approaches. © 2009 The Institution of Engineering and Technology.	en
heal.publisher	INST ENGINEERING TECHNOLOGY-IET	en
heal.journalName	IET Computers and Digital Techniques	en
dc.identifier.doi	10.1049/iet-cdt:20080009	en
dc.identifier.isi	ISI:000264048800006	en
dc.identifier.volume	3	en
dc.identifier.issue	2	en
dc.identifier.spage	205	en
dc.identifier.epage	221	en