TELIOS: A tool for the automatic generation of logic programming machines

Dimopoulos, AC; Pavlatos, C; Papakonstantinou, G

dc.contributor.author	Dimopoulos, AC	en
dc.contributor.author	Pavlatos, C	en
dc.contributor.author	Papakonstantinou, G	en
dc.date.accessioned	2014-03-01T01:32:02Z
dc.date.available	2014-03-01T01:32:02Z
dc.date.issued	2009	en
dc.identifier.issn	15715736	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/20031
dc.subject	Automatic Generation	en
dc.subject	Logic Programs	en
dc.title	TELIOS: A tool for the automatic generation of logic programming machines	en
heal.type	journalArticle	en
heal.identifier.primary	10.1007/978-1-4419-0221-4_61	en
heal.identifier.secondary	http://dx.doi.org/10.1007/978-1-4419-0221-4_61	en
heal.publicationDate	2009	en
heal.abstract	In this paper the tool TELIOS is presented, for the automatic generation of a hardware machine, corresponding to a given logic program. The machine is implemented using an FPGA, where a corresponding inference machine, in application specific hardware, is created on the FPGA, based on a BNF parser, to carry out the inference mechanism. The unification mechanism is based on actions embedded between the non-terminal symbols and implemented using special modules on the FPGA. © 2009 International Federation for Information Processing.	en
heal.journalName	IFIP International Federation for Information Processing	en
dc.identifier.doi	10.1007/978-1-4419-0221-4_61	en
dc.identifier.volume	296	en
dc.identifier.spage	523	en
dc.identifier.epage	528	en