A methodology for alleviating the performance degradation of TMR solutions

Siozios, K; Soudris, D

dc.contributor.author	Siozios, K	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T01:32:28Z
dc.date.available	2014-03-01T01:32:28Z
dc.date.issued	2010	en
dc.identifier.issn	19430663	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/20143
dc.subject	Fault tolerance	en
dc.subject	reconfigurable architecture	en
dc.subject	reliability	en
dc.subject	triple modular redundancy (TMR)	en
dc.subject.other	Fault masking	en
dc.subject.other	High density	en
dc.subject.other	In-field	en
dc.subject.other	Mitigation costs	en
dc.subject.other	Performance degradation	en
dc.subject.other	Power degradation	en
dc.subject.other	Process Technologies	en
dc.subject.other	Reconfigurable architecture	en
dc.subject.other	Reliability improvement	en
dc.subject.other	Transient faults	en
dc.subject.other	Triple modular redundancy	en
dc.subject.other	Degradation	en
dc.subject.other	Fault tolerance	en
dc.subject.other	Fault tolerant computer systems	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	Redundancy	en
dc.subject.other	Software reliability	en
dc.subject.other	Quality assurance	en
dc.title	A methodology for alleviating the performance degradation of TMR solutions	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/LES.2010.2083632	en
heal.identifier.secondary	http://dx.doi.org/10.1109/LES.2010.2083632	en
heal.identifier.secondary	5597921	en
heal.publicationDate	2010	en
heal.abstract	The shrinking of process technologies in conjunction to the manufacturing and transient faults may be abundant in high density reconfigurable architectures. Design of reliable applications on such unreliable architectures requires techniques able to provide a balance between the desired fault masking and the associated performance and power degradation. Starting from a well established solution for reliability improvement in field-programmable gate arrays (FPGAs) domain, we discuss a software-supported methodology that removes redundancy as much as possible from the design without affecting it's efficiency in terms of fault masking. Based on experimental results, our proposed methodology achieves comparable fault masking with commercial solutions, but in reasonable lower mitigation cost. © 2010 IEEE.	en
heal.journalName	IEEE Embedded Systems Letters	en
dc.identifier.doi	10.1109/LES.2010.2083632	en
dc.identifier.volume	2	en
dc.identifier.issue	4	en
dc.identifier.spage	111	en
dc.identifier.epage	114	en