Efficient implementation of a frame aggregation unit for optical frame-based switching

Kornaros, G; Sund, M; Lautenschlaeger, W; Leligou, H-C; Orphanoudakis, T

dc.contributor.author	Kornaros, G	en
dc.contributor.author	Sund, M	en
dc.contributor.author	Lautenschlaeger, W	en
dc.contributor.author	Leligou, H-C	en
dc.contributor.author	Orphanoudakis, T	en
dc.date.accessioned	2014-03-01T01:33:20Z
dc.date.available	2014-03-01T01:33:20Z
dc.date.issued	2010	en
dc.identifier.issn	1434-8411	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/20382
dc.subject	Hardware implementation	en
dc.subject	High speed networks	en
dc.subject	System-on-chip architecture	en
dc.subject	Traffic aggregation	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.classification	Telecommunications	en
dc.subject.other	10 Gb/ S	en
dc.subject.other	A-frames	en
dc.subject.other	Assembly process	en
dc.subject.other	Core networks	en
dc.subject.other	Core nodes	en
dc.subject.other	Efficient implementation	en
dc.subject.other	Ethernet frames	en
dc.subject.other	Hardware implementation	en
dc.subject.other	Hardware implementations	en
dc.subject.other	IP packets	en
dc.subject.other	Optical frames	en
dc.subject.other	Quality of Service parameters	en
dc.subject.other	Queue managers	en
dc.subject.other	System-on-chip architecture	en
dc.subject.other	Traffic aggregation	en
dc.subject.other	Application specific integrated circuits	en
dc.subject.other	Cellular radio systems	en
dc.subject.other	Ethernet	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	HIgh speed networks	en
dc.subject.other	Jitter	en
dc.subject.other	Network architecture	en
dc.subject.other	Programmable logic controllers	en
dc.subject.other	Quality control	en
dc.subject.other	Quality of service	en
dc.subject.other	Hardware	en
dc.title	Efficient implementation of a frame aggregation unit for optical frame-based switching	en
heal.type	journalArticle	en
heal.identifier.primary	10.1016/j.aeue.2008.09.009	en
heal.identifier.secondary	http://dx.doi.org/10.1016/j.aeue.2008.09.009	en
heal.language	English	en
heal.publicationDate	2010	en
heal.abstract	Aggregating Ethernet frame or IP packet in large fixed-size frames allows for building scalable core network architectures. Classifying the arriving traffic based on destination core node information and quality of service parameters alleviates the need of performing table look-ups on packet basis. These advantages come at the cost of extra logic at the network egress, as regards implementation, and additional jitter due to the frame assembly process. This paper describes the efficient implementation of a frame aggregation unit that gathers Ethernet packets in G.709 containers, handles 10Gb/s links, performs classification based on 24-byte headers, and includes a highly pipelined Queue Manager to cope with the considered rates while a specific scheduler controls the quality of service per core network flow. Based on the developed demonstrator, we provide results both as regards area and performance for an FPGA (field programmable gate array) Virtex-4 implementation as well as regarding the introduced jitter. (C) 2008 Elsevier GmbH. All rights reserved.	en
heal.publisher	ELSEVIER GMBH, URBAN & FISCHER VERLAG	en
heal.journalName	AEU - International Journal of Electronics and Communications	en
dc.identifier.doi	10.1016/j.aeue.2008.09.009	en
dc.identifier.isi	ISI:000273890200003	en
dc.identifier.volume	64	en
dc.identifier.issue	1	en
dc.identifier.spage	17	en
dc.identifier.epage	28	en